India's teaching community contemplates SoC design

The VLSI Society of India recently organized a two-day faculty development workshop on SoC design, — Train-the-Trainer program — on Oct. 30-31, 2010, at the Texas Instruments India office, in co-operation with PragaTI (TI India Technical University) and Visweswaraya Technological University (VTU).

Dr. C.P. Ravikumar, TI, addressing the teachers at the workshop.

Dr. C.P. Ravikumar, TI, addressing the teachers at the workshop on SoC design.

I am highly obliged and very grateful to the VLSI Society of India and Dr. C.P. Ravikumar, technical director, University Relations, Texas Instruments India, for extending an invitation. Here is a report on the workshop, which the VSI Secretariat and Dr. Ravikumar have been most kind to share.

System-on-chip (SoC) refers to the technological revolution, which allows semiconductor manufacturers to integrate electronic systems on the same chip. System-on-board, which has been the conventional implementation of electronic systems, uses semiconductor chips soldered onto printed circuit boards (PCBs) to realize system functionality.

Systems typically include sensors, analog frontend, digital processors, memories and peripherals. Thanks to the advances in VLSI technology, these sub-systems can be integrated on the same chip, reducing the footprint, cutting down the cost, improving the performance and power efficiency.

While the industry has adopted SoC design for many years, the academic community around the world (India not being an exception) has not caught up with the state-of-the-art. Electrical/electronics engineering departments continue to teach a course on VLSI design, where the level of design abstraction is device-level, transistor-level, or gate-level.

Register-transfer-level (RTL) design using hardware description languages is taught in some Masters’ programs, but colleges often do not have the lab infrastructure to carry out large design projects; very few Indian universities have tie-ups with foundry services to get samples. A semester is too short a time to complete a large project.

The complexity of modern-day design flow is not easy to impart in a single undergraduate course. Masters’ programs are particularly relevant in VLSI, but the M.Tech programs in the country languish due to several reasons.

Ground realities
“M.Tech programs do not attract top students who are highly motivated,” said a professor who attended the two-day faculty development program organized by VLSI Society of India. “Almost all undergraduate programs today have a course on VLSI technology and design. But since we get students from different backgrounds, they do not have the pre-requisites. So, a course on VLSI design at M.Tech level will have a significant overlap with an undergraduate course on VLSI design.”

“Faculty members need training,” said another teacher. “When a new course is introduced, significant time is needed for preparation.  Prescribed textbooks for a new course are often not available. Internet search for course materials often returns too much material and it is hard to decide what to use. Colleges that have autonomy can decide their own curriculum, but in a university setup, the faculty face a major challenge. We are evaluated on how well our students fare in the exams. Yet, our students have to face an exam made by a central committee.”

“Having a common exam poses many problems in setting up a relevant question paper. The format of the question paper is fixed. The students get a choice of answering five questions from a set of eight. Due to the common nature of the question paper, the questions tend to demand descriptive answers.”

Faculty development workshop on SoC design
About 30 faculty members interested in system-on-chip design took part in the faculty development workshop. The attendees came from about 25 different colleges from VTU, VIT University, and Anna University. The workshop was conducted in co-operation with the Viswesaraya Technological University (VTU) and sponsored by Texas Instruments, India.

The premise for the workshop was that a course on SoC design is required at the Masters’ level, since industrial practice has clearly moved in that direction. The RTL-to-layout flow, which continues to be relevant for IPs that constitute an SoC, aspects of SoC design, which relies on IP integration, are not covered in any course.

The workshop provided a forum for industry-academia interaction. Several professionals from the industry took part in the workshop and answered questions from the faculty members. 

Dr. Subir Roy, TI, discusses some formal verification techniques.

Dr. Subir Roy, TI, discusses some formal verification techniques at the workshop.

Dr. C.P. Ravikumar, Sarveswara Tammali and Dr. Subir Roy of Texas Instruments, and Raghu Kodali (ARM), took part in the workshop. Dr. C.P. Ravikumar co-ordinated the workshop and explained the motivation for SoC design in general and for the workshop in particular.

Sarveswara Tammali spoke on the topic of “Design for Testability” as applied to SoC. Dr. Subir Roy spoke about the topic of functional verification of SoC.

Raghu Kodali used the example of ARM Cortex-M3 to discuss the entire IP design flow. Apart from the tutorial value of the presentations made at the workshop, the faculty gained through interaction with professionals as well as the discussion on the challenges of teaching advanced topics and the sharing of solutions.

Homework-oriented workshop
At the end of day 1, faculty members received “homework” of identifying the topics that they would include in the seven sections of a course on SoC design.

The faculty presented their ideas on Day 2 and through lively debates were able to align on the teaching materials, the kind of seminars the students can be asked to give as part of the course, the kind of mini-projects that can be given to students, and typical questions that can be included in the course.

Professional development opportunities
Prof. C.R. Venugopal, chairman of the Board of Studies, VTU, advised the faculty members on career development opportunities.

He said: “Becoming a member of a professional society such as the IEEE, IET, or VSI can open up many doors in personal and professional development. I have been mentoring the IEEE Student Chapter at SJCE Mysore. I have also been regularly attending the VLSI Design and Test symposium organized by the VLSI Society of India. These have provided me great opportunities to network with professionals from the industry. There are also many opportunities for submitting research proposals with the university as well as to national bodies that promote academic R&D.”

“The workshop has allowed faculty members to come together to engage in a healthy debate, seek/propose solutions to their problems,” was one of the several enthusiastic feedbacks for the workshop.

It was also decided that a website will be created to share the proceedings of the workshop as well as the links to teaching materials for a course on SoC design.

  1. Dr. M.P. Divakar
    November 4, 2010 at 6:34 pm

    Pradeep: It is good to see another posting from you on a topic that is quite relevant today, not to mention interesting to me personally!

    You have brought to the fore several limitations of teaching SoC design in an academic environment. The time limitations in a semester system is a big one, but the faculty needs to get a little creative in addressing this.

    It is a lot easier if there is a fab-lite co-op entity like Mosis (in the LA area) that can turn around designs in four weeks or less in shuttle runs (MPW’s) or dedicated full wafer runs. And, if you make effective uses of wafer splits (at contact), it is possible to cut short the overall time to first silicon.

    More importantly, I did not see an emphasis on holistic aspects of SoC design; covering discussions IPs, verification, synthesis, RTL-to-GDS is all great, but post silicon is equally important.

    The students need to understand an end-to-end design flow all the way to packaging and final test, while not necessarily becoming experts of back end design!

    SoC design is truly multidisciplinary and with the evolving 3D chip designs, this is more relevant at the design stage today than ever before. Add to this, hands on experience in characterising first silicon is crucial. I have come across way too many ‘VLSI Design Experts’ from India that have never been to a lab!

    Say hello to Prof. C.R. Venugopal (I was his colleague at my alma mater, SJCE, Mysore) when you see him next. Importantly, let him know that there are many of us willing to help. I am glad to see the academic community (particularly the non-IIT) in India taking a leading role in teaching SoC design.

    However, I disagree with the statement above that says the academic community around the world (India not being an exception) has not caught up with the state-of-the-art SoC design; this is simply not true in the US and many European countries. Regards.

    Dr. MP Divakar

  2. November 4, 2010 at 6:41 pm

    Thanks a lot, Sir 🙂 The VLSI Society of India and Dr. Ravikumar must be thanked and congratulated for the excellent work. Regards and Happy Diwali 🙂

  3. Hillol Sarkar
    November 5, 2010 at 6:42 am

    India SoC Development

    1. Knowledge

    2. Job

    Need more hardware companies in India to serve the Indian market.

    Anurag is a good project. IP is available to build sysytem.

    It is not required to build a chip. You can use FPGA to build prototype.

    University should create environment for new product creation.

    Ref: Lte Base Station Building block:

    Ref: Music Engineering using NVIDIA


    1. Digital – No problem, many options.

    2. Analog:

    DoD and Science Foundation have created many key products including Internet.

    Anurag can play vital role in VLSI development and new product creation.

    China – Very week in creating software products. India has the advantage.

    Market segment to focus:

    1. LTE-A.
    2. Wireless LED – high volume business model – invent new products.
    3. M2M – Healthcare service without using hospitals.
    4. M2M – Build modern logistics to reduce leakage.

    Hillol Sarkar
    CEO, AgO Inc.

    • November 5, 2010 at 9:57 am

      Thanks a lot, Hillol sir. Indeed, there is a pressing need for having many, many more hardware companies in India. Also agree with the thought of developing an environment that nurtures, supports and enhances product creation and development, especially in the institutions.

      Happy Diwali to you and your family! 🙂

  4. Dr. C.P. Ravikumar
    November 5, 2010 at 9:34 am

    Dear Dr. Divakar,

    This particular workshop focussed on a course called “SoC Design,” which is being considered (for the first time) as an graduate-level course in an M.Tech program on “VLSI and Embedded Systems”. Such an M.Tech program is a two-year program with several courses.

    Typically, fault models/design for test/test generation are taught as a separate course in the M.Tech programs. We did include a talk on SoC test as part of the workshop. We welcome your view points on how an M.Tech program in VLSI design/embedded systems should be structured, what should be “core,” and what should be “elective.”

    While we have that debate, we must keep in mind the industry-relevance of the program and the employability of the graduating engineers in the (Indian) semiconductor industry.


    Dr. C.P. Ravikumar
    Secretary, VSI.

    • November 5, 2010 at 9:55 am

      Thanks a lot, sir! It is a pleasure and honor to be part of this initiative.

      Wishing you and family a very happy and joyous Diwali! 🙂

  5. sujatha
    November 6, 2010 at 8:32 am

    Dr C.P. Ravikumar sir,

    I have attended the SoC design program from Anna University, Chennai. The program was very useful to me. Thank you for conducting such a program. I will be very pleased if you could inform me about the forthcoming programs here afterwards.

    Wishing you happy Diwali.


  6. Dr. C.P. Ravikumar
    November 6, 2010 at 1:36 pm

    Dear Prof. Sujatha,

    Thanks for your comment. Wish you a very happy Diwali too! We will keep you posted about more activities.

    We are also compiling the materials from the workshop and will share them with the participants. Feel free to send in your thoughts about any of the aspects that were discussed at the workshop.


    Dr. C.P. Ravikumar

  7. Dr. G S Jayadeva
    November 8, 2010 at 4:59 am

    Dear Dr. C P Ravikumar,

    Thanks for well organized course on ‘SoC’. The course gave us the path to start teaching the course for M.Tech students.


    • Dr. C.P. Ravikumar
      November 8, 2010 at 9:35 am

      Dear Dr. Jayadeva,

      Thanks for your comment. I enjoyed the workshop – the faculty participated enthusiastically. We are in the process of putting together the materials presented at the workshop. I expect to be able to share them with the participants soon. Wish you all the best.


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