Cadence Virtuoso IC6.1.4 design platform comes with several enhancements

Last week, Cadence Design Systems Inc. introduced the Virtuoso IC6.1.4 — with dramatic improvements to the Virtuoso IC design platform — that reduces overall design time and ensures high-quality production ICs.

These enhancements are said to benefit design teams working along the full spectrum of design complexity, from the most advanced-node, cutting-edge designs to more traditional chips.

This release has been extended to work efficiently at advanced nodes down to 28 nanometers and now supports 64-bit processing for improved capacity and performance. The Virtuoso Space-Based Router has been integrated into the Virtuoso Layout Suite cockpit, making it easier to access.

I got into a conversation with Steven Lewis, marketing director, Cadence, to find out more about this release.

Steven Lewis, marketing director, Cadence Design Systems.

Lewis said: “Virtuoso IC61 was first shipped in October, 2006, over three years ago. IC614 is the latest release of this platform. IC61 is based on OpenAccess as a database with a Qt based GUI. Also, in IC61 a common design constraint system is key to design spanning schematics, layout, routing, circuit optimization, and all other Virtuoso applications.”

The IC 614 has a number of significant areas of enhancements. These include:

1) Significant improvements to analog design environment — A number of key enhancements have gone into ADE to make it even easier to use and to improve performance. Areas like: data presentation, multi-testbench support, analysis and signoff quality validation, data sheet generation, simulation results comparisons, and intelligent selection of sensitivity to statistical variations to dramatically reduce the number of simulations needed.

2) Native integration of the Catena interconnect engine — This enables integration of the Cadence Space-based Router into VLS-GXL, including the common design-constraint system, runtime OA database and OA techfile for design rules. In addition, the Wire Editor, which is based on this technology, is available to every VLS XL Layout Designer.

3) Metric-Driven Productivity — IC 6.1.4 is all about productivity, productivity, productivity. Many users of VLS spend six to eight hours a day in front of this cockpit and incremental improvements have a significant cumulative effect. IC 6.1.4 will:
* Reduce the mouse miles that a layout designer sees.
* Reduce the mouse clicks required for an operation.
* Reduce the menu depth for an operation.

And, how will the IC6.1.4 gain capacity, performance and usability boosts to shrink design cycles?

According to Lewis, there are a number of enhancements to frequently used features, like a new Layer Palette, improved Repeat Copy, enhancements to Via Placement, a new Smart Ruler, and PCell Caching. Additionally, there are improvements to the connectivity, constraint-aware editing and verification, and capacity with the 64-bit port.

Cadence's Lip-Bu Tan on global semicon, EDA and Indian semicon industry

Lip-Bu Tan, president and CEO, Cadence Design Systems Inc.

Here is an Outlook 2010 report on the global semiconductor industry, as well as the EDA industry, and a look at what lies ahead for India.

Lip-Bu Tan, president and CEO, Cadence Design Systems Inc., who was recently in India during the CDNLive event, is of the opinion that the global semiconductor industry is undergoing some significant changes that will further place new demands on the EDA providers.

Semicon industry trends
Speaking on the current trends in the global semiconductor industry, he said: “Semiconductor companies are becoming more focused on their core competencies, and are increasingly collaborating on a global basis. They are prioritizing capital efficiency, and they are looking for help in containing the costs of both hardware and software development.”

With the emphasis on profitability, one trend that will continue to occur is consolidation. Semiconductor companies are consolidating in order to scale existing businesses, to grow by complementing existing product lines and to focus on strategic, differentiated or market-leading areas, and of course, to save costs.

He added: “The trend towards “fab lite” continued in 2009. AMD spun off GlobalFoundries, its Dresden, Germany fabrication facility, and the parent company of GlobalFoundries, based in Abu Dhabi, announced its intention to acquire Chartered Semiconductor. It appears that if this trend continues, there will be fewer integrated device manufacturers (IDMs) and fewer semiconductor manufacturers in the future, as fab costs for advanced processes soar.

“Globalization is another trend that will accelerate as economies become more interdependent. It can aid recovery, given that stimulus packages can be expected to uplift most major economies. Today, the best growth prospects appear to be in the developing countries.

“Success at globalization requires some new thinking. Companies must think “locally” in places they operate, taking advantage of local supply chains, markets, partners, and engineering talent. Cost optimization is a likely consequence of moving some operations offshore, but if it’s the only motivation, companies are likely to be disappointed. It is important that the business strategy drives globalization, not the other way around.

“Beyond consolidation and globalization, as I indicated earlier, collaboration may also continue to pick up speed. The design challenges at 45nm and below will shape the semiconductor ecosystem in 2010 and beyond. Technical challenges include process variability, signal integrity, design for manufacturability, timing closure, analog/mixed-signal circuitry, and low-power design. Solutions will require extensive collaboration between EDA, silicon IP, semiconductor, and foundry companies – no single company can do it all.

Global re-optimization of industry
Quite interesting, that Tan mentioned industry consolidation. Will there be further consolidations within the industry?

According to him, we have seen consolidation within the semiconductor industry in 2009 and it has been global in nature. What is occurring is a kind of global re-optimization of the industry. IC design, manufacturing, test, packaging, and product assembly are taking place in many different parts of the world, with multiple companies and geographically dispersed teams.

“Although, I think, we may see further consolidation in the coming year; beyond that, I can’t speculate on who will participate or when that will happen.”

Semicon industry outlook for 2010!
How is the outlook for 2010 going to shape up now that some signs of recovery have appeared?

Lip-Bu Tan said that according to the Semiconductor Industry Association (SIA), after a decline of over 11 percent in 2009 as compared to 2008, the semiconductor industry is projected to grow by over 10 percent in 2010 and 8.4 percent in 2011.

“While an economic recovery is inevitable, and may already be taking shape, customers still remain cautious in their optimism. They are keeping a tight rein on research and development budgets. This is consistent with what we have seen with other downturns, and we expect the EDA industry recovery to lag a quarter or two behind the semiconductor industry.”

Indian EDA thought leaders can exploit opportunities from tech disruption!

Wesley Ryder, Worldwide Technical Director, Mentor Graphics.

Early April, I had met Wesley Ryder, Worldwide Technical Director, Mentor Graphics, along with Hanns Windele, VP Europe and India, Mentor, during an event organized by the India Semiconductor Association (ISA). Both were back in India recently– for Mentor’s User2User conference, where Ryder delivered the keynote: Carpe diem – Golden opportunities for India to shine!

According to Ryder, India has all the ingredients to exploit opportunities from technology disruption. Inda, according to him, has a young, open-minded workforce – not blinkered by old methods. Also, this workforce has the ability to see opportunities and take measured risks. Besides being high quality, skilled individuals, they are also (EDA) thought leaders.

Implications for EDA and India
Given this scenario, what are the implications for EDA? Ryder said these are:
* Introduce and support leading-edge design tools in India.
* EDA startups focus more initial sales efforts in San Jose and India.
* Purchasing decisions increasingly incorporate India design teams to drive flows and decisions.
* India emerges as the test bed for new design ideas.

And what are the implications for India? Ryder advises Indian designers to:
* Exercise your influence—demand best in class design tools and capabilities.
* Always remain open to new design approaches,
— Beware of becoming risk adverse as you become more experienced.
— Stay abreast of emerging innovations by maintaining close contact with EDA companies, including start-ups.
* Make your EDA suppliers aware of your issues and challenges.

Giving an overview regarding the adoption of disruptive new technologies and the evolution of EDA, Ryder said many electronic engineers do not consider themselves “risk takers.” Most electronic engineers don’t seem to like to change tools either, unless there is a major advantage in price or performance. As a result, many will not even consider “hot” new tools.

However, it has been observed that inexperienced engineers and recent university graduates eagerly adopt new technology. It provides them a way to distinguish themselves, besides the productivity advantage. Also, they are less invested in existing methodologies.

Among designers with five to 15 years of experience, it was observed  that some were reluctant, but afraid to be left behind. Some others were intimidated by new college graduates. However, the smartest, most aggressive designers made the change relatively quickly. Many delayed transition, waiting for mature tools.

India a fertile environment for new tech adoption
So what makes a fertile environment for new technology adoption? A young, open-minded workforce, which can see opportunities and take measured risks, and those who are highly skilled and thought leaders!

Ryder said that the the age of electronic engineers in India is lower than all other major design locations. It is 46 years in the USA, 45 in Japan, 41 in Europe, 35 in Korea, 34 in Taiwan, 31 in China and 30 in India! Hence, the tenure is lower and designers are not blinkered or bothered by old methods. He added that India’s engineers place a high priority on staying current, learning and continuing education.

He cited a quote of Rich Templeton, president and CEO, Texas Instruments, who said about India: “The reason we are here is very simple — and that is to get access to really great people.” He added: “TI India is an integral part of our worldwide development strategy in bringing about, stateof-the-art products and technologies for our customers globally. Over the years, India has come to play an increasingly important role in the long-term success of TI.”

Ryder contended that electronic designers in India, on average, are as smart as those from United States, Europe and Japan.

Disruption creates opportunity and there is an increasing influence of India design centers. For instance, Indian designers were early adopters of C-based design. Also, place and route was increasingly being carried out in India (and DFT + verification). In functional verification, India also has deep expertise in modeling.

With such EDA thought leaders in place, India possesses all of the necessary ingredients to exploit opportunities from technology disruption.

Lip-Bu Tan, president and CEO, Cadence, on global semiconductor trends

Lip-Bu Tan, president and CEO, Cadence Design Systems @ CDNLive in Bangalore, India.

I recently attended Cadence Design Systems’ CDNLive event in Bangalore this week. Here’s a snapshot of Lip-Bu Tan, president and CEO, Cadence, touching upon global semiconductor trends during his keynote address.

According to Tan, the semicon industry is recovering and stabilizing, and gradually improving. The semiconductor revenue is also improving, but is still down, as compared to last year.

JP Morgan conducts a CEO survey with the GSA (Global Semiconductor Association), known as the Semicon CEO Sentiment Index. It shows that the CEO sentiment has improved from 29 percent in Jan. 2009 to 51.4 percent in Oct. 2009.

Innovative products are most likely to drive recovery. These include 4G phones, smart grid power, medical electronics and emerging markets. In 4G, WiMAX is growing, while in smart grid, semiconductors play a critical role. Medical electronics is also growing rapidly, and emerging markets such as China and India are very important. Video traffic is another big market.

SoCs facilitate innovative products and capital efficiency
How will you deliver innovative products? Perhaps, by capital efficiency! You require to develop very close partnerships with your foundry partners. IP or intellectual property is becoming very important as well. For example, a complex chip could well have over 50,000 IPs that would need to be integrated. There are EDA tools as well.

SoCs facilitate the delivery of innovative products and capital efficiency. Advantages of the SoC include developing multifunction devices, allowing the setting of aggressive price targets, and also developing products in innovative form factors. SoC designs are leading the industry. Most chips are today mixed signal in nature.

An example is the iPhone, which has several SoCs. It uses a very complex chip that integrates everything and runs on low power.

Implications of SoC development and integration
The implications of SoC development and integration include collaboration, mixed signal and system-level design and verification. SoCs require extensive collaboration.

Software will be driving the differentiating factors. Next, all SoCs are mixed signal designs. Incidentally, Cadence is a leader in mixed signal. SoCs also require a system level of improvement. Cadence has solutions for system level design and verification.

Later, Cadence will move into virtual prototyping. This will help the company in moving forward as per its roadmap. Cadence delivers leadership core products, and complements those products with the ecosystem and service offerings. “Our foundation business — we want to be SoC realization partner with our customers,” said Tan.

Here are some announcements from Cadence at CDNLive:
* TLM-to-GDS design and verification flow announced.
* 450+ customers for RTL Compiler and Conformal.
* Customers switching to OVM for verification re-use.
* Encounter adds 230+ new customers.
* Virtuoso speeds Spectre simulation up to 60 percent for mixed signals.

Lip-Bu Tan said that Cadence is a trusted and open EDA partner of the electronics industry, and is committed to the leadership technology creation. It will deliver and enable leading solutions in SoCs. Cadence is also organizing to optimize in efficiency creation and delivery of its offerings globally.

“We are committed to our customers’ success. The key is to find the right role within the ecosystem. We are again profitable as well, with $570 million in cash,” he concluded.

 

Mentor's Wally Rhines on EDA industry — II

Friends, this is a continuation of my conversation with Walden (Wally) C. Rhines, chairman and CEO, Mentor Graphics Corp., who was recently on a visit to India for the EDA Tech Forum as keynoter.

Software-to-silicon verification

Today there’s a growing focus on software-to-silicon verification, encompassing a full range of challenges that also includes embedded software, system validation and integration testing. How true?

Certainly true! The problem of hardware/software codesign and co-verification has been around a long time but, until this decade, generated less than $50million of annual EDA revenue.

Rhines said: “This decade, the market has grown rapidly and companies like Mentor have experience accelerated revenue growth in both their ESL design environments and their embedded software development tools and technology. Emulation has grown increasingly popular to verify not only hardware but to test application/embedded software.

“And, embedded software development tools, technology, RTOS, protocol stacks and LINUX middleware have all become part of the electronic product developers design environment.”

EDA in modeling and photomask correction

How and where does EDA fit into the big picture, particularly in the areas of modeling and photomask correction?

According to Rhines, for photomask correction, the EDA industry is the only provider, with two large EDA companies providing more than 90 percent of the optical proximity correction revenue.

“EDA companies have changed over the last decade due to the growth of OPC and DFM. Wafer fabs have now become major customers. Specialists in optics have joined traditional electronic design specialists at EDA companies to create the key technologies. EDA companies are now leading the way in the development of new process technology as evidenced by the IBM/Mentor joint development program at 22nm, he added.

Mentor's Wally Rhines on global EDA industry and challenges

Walden C. Rhines, chairman and CEO, Mentor Graphics Corp.

Thanks to Veeresh Shetty at Mentor Graphics, I was very fortunate to get into a conversation with Walden (Wally) C. Rhines, chairman and CEO, Mentor Graphics Corp., who was recently on a visit to India for the EDA Tech Forum as keynoter.

Besides discussing the global EDA industry, the challenges it is currently facing, we also discussed industry issues such as whether the lack of EDA tools is a bottleneck for 3-D implementation, EDA in the big picture, with regard to areas such as modelling and photomask correction, and so on.

State of global EDA industry
According to Walden Rhines, 2008 and the first quarter of 2009 are the weakest periods ever reported by the EDA industry.

He said: “A substantial portion of the weakness during this period was caused by a change in revenue recognition accounting by one of the major EDA companies. Before 2008, there had only been two years of negative EDA revenue growth in history and both of those were very minor negatives (i.e., almost zero) and both of those were caused primarily by changes in revenue recognition accounting, one each by each of two major EDA companies.”

While this recession is the most precipitous drop in electronics industry history, the normal pattern of preserving most R&D spending has been maintained by most electronics companies. As a result, the decline in EDA revenue is small when compared to the decline in semiconductor industry revenue.

“As the electronics industry recovers, and its R&D spending once again comes in line with its growing revenue, the EDA industry should recover as well. Positive signs include the strength of the semiconductor sequential revenue growth in Q209 and the fact that the Q109 rate of year to year decline in EDA revenue was nearly half the rate of decline of the fourth quarter of 2008,” he added.

Tech challenges
What would be the biggest technical challenges facing the EDA industry right now? Rhines said that the largest technical challenges for the EDA industry right now are:

1) low power design (from system level through physical layout),

2) keeping up with the growing functional verification challenge (by developing new approaches including ESL, coverage based verification, emulation, intelligent testbench, hardware acceleration of test benches, assertion-based verification, etc.) and

3) dealing with manufacturing variability (through application of design-for-manufacturing techniques to design).

The conversation continues in a while… I’ll be back!

Rapidly growing local market bring new opportunities for EDA in India

Those following the EDA industry are well aware that its been an industry in some trouble right through this year.

If you visited EDA Consortium’s web site, this becomes clear. In Q1-08, the global EDA industry revenue for Q1 2008 declined 1.2 percent to $1,350.7 million compared to $1,366.8 million in Q1 2007.

Later, the EDA industry revenue for Q2 2008 declined 3.7 percent to $1357.4 million compared to $1408.8 million in Q2 2007, as reported by the EDA Consortium.

I am still waiting to see how the Q3 results shape up. My guess is, it would be even lower than Q2, unless there are a few surprises!

The EDA market in India, as per the ISA F&S Report 2005, was US$110m. The latest figures are not yet available, though I would believe the Indian EDA industry is likely to do better than the global industry, unless, there have been some slowdown effects here as well.

I had an interesting discussion with Jaswinder Ahuja, Corporate Vice President and Managing Director, Cadence Design Systems (I) Pvt. Ltd and Chairman, India Semiconductor Association (ISA), on the (dipping?) fortunes of the EDA industry lately.

According to Ahuja, 2008 has been a challenging year. The global financial crisis has impacted several industries and the EDA industry was no exception. Due to the overall downturn in the economy, companies are being more cautious and are delaying purchase decisions, a move that is impacting the overall EDA industry.

Coming to the drivers for EDA in India this year, there are a few key ones! First, the design centres have gained expertise and are now doing cutting-edge designs out of India. They have moved up the value chain from doing block-level design to increasingly owning up end-to-end design and design starts.

Second, several Indian design services companies have made significant acquisitions, showing that their businesses have not just taken root, but also flourished. MindTree Consulting’s acquisition of TES PV and Wipro’s acquisition of Oki’s wireless chip design arm are cases in point, added Ahuja.

He said: “The Indian EDA industry has been growing and we will see more technology adoptions and proliferations in India Design Centers. Also, the rapidly growing local market is unfolding new opportunities.”

EDA outlook 2009
Going forward, market pressures and design complexities are just some of the issues design teams face today. Cadence’s customers, for instance, would like to plan in the context of IP selection, run analysis around power, performance and cost perspectives. Design predictability will be a priority, said Ahuja.

The key focus areas for the EDA industry will be new design for manufacturing technologies as designs move to advanced nodes; verification and verification IPs and multicore processing support for EDA flows as a result of increased integration.

Also, SaaS is likely to gain traction as companies are compelled to consider flexible engagement models to access state-of-the art design environments that help design teams reduce risk and cost, yet increase time-to-productivity.

Are there any opportunities for EDA folks in solar? Ahuja disclosed that in a recent poll by ISA, to the question ‘Solar PV has potential in India’, almost 90 percent of respondents replied Agree or Strongly Agree.

With the worldwide focus on alternative energy systems, India has witnessed several companies announcing investments in PV segment. This is good news for the Indian semiconductor ecosystem.

Cadence has a broad portfolio of technologies that addresses the needs of different players in the ecosystem.

Low power initiatives
Low power has always been a key focus area in semiconductors. According to Ahuja, power efficient design is gaining importance across the design chain and EDA companies will have to look closely at ‘green’ technologies.

Energy efficiency at the system and application level for wired and wireless products will be one of the focus areas. Emerging technologies that allow applications and systems developers to evaluate how their programs use power both individually and in a dynamic, multi-application model of the end system will help expand the role of EDA into system-level design.

The Power Forward Initiative (PFI), an industry alliance comprising of companies across the semiconductor design chain will work towards a more systematic, integrated approach to low-power design.

Outlook 2009
With the new year about to start in less than a week’s time, the impact of the financial crisis will see an increased demand for mid-range product technology as consumers shift spend toward ‘essential’, rather than ‘desirable’ electronic products.

As per Ahuja, globally, semiconductor companies are focusing on their core strengths, consolidating and realigning resources. Across sectors, they will look for systems that marry functionality with cost efficiencies.

“Growth for semiconductor companies will come from energy related and low-power technologies that are able to drive market share shifts,” he noted.

Cadence's Virtuoso vs. Synopsys' Galaxy Custom Designer!

Synopsys recently introduced the Galaxy Custom Designer, which provides a unified solution for custom and digital designs, thereby enhancing designer efficiency.

Well, this solution invariably draws a comparison with Cadence’s Virtuoso platform within the EDA industry!

That prompted me to engage Sandeep Mehndiratta, Product Marketing Group Director, Cadence Design Systems, in this discussion. We discussed a range of issues, such as how the Synopsys’ Galaxy Custom Designer matches up with the Virtuoso, and whether designers can now design what they wish, including concepts and flows, as well as the relevance of open architectures.

For the record, a few years ago, Cadence introduced the next-generation Virtuoso custom design IC 6.1 platform, which had a major upgrade recently with the IC 6.1.3 release. This release has been production-proven with tapeouts from many customers. However, as I said, it is Synopsys’ Galaxy Custom Designer doing the rounds in the EDA circles as of now!

Galaxy Custom Designer vs. Virtuoso
It is well known that Cadence has been the established leader in custom IC design space for decades, and has been constantly improving and upgrading technology to ensure it is providing best-in-class platform for designing today’s complex custom chips.

Mehndiratta said: “A couple of years ago we introduced the next-generation Virtuoso custom design IC 6.1 platform. This release has been production-proven with tapeouts from many customers. Some of the leading customers that have adopted the Virtuoso platform include Ricoh, National Semiconductor, Cambridge Analog Technologies Inc., Matsushita, etc.

“Synopsys has recently launched Galaxy Designer and it is unproven as yet. From what we’ve read and heard from some of our mutual customers, the competitive introduction may be attempting to replicate older custom IC technology. While the jury will probably be out for some time on this unproven tool, Cadence continues to provide a complete solution for design, verification and implementation of complex analog and mixed-signal designs, differentiated by the tight integration between the underlying technologies.”

With the advent of Galaxy, is it now safe to say that designers can finally design what they wish, including concepts and flows? Well, the answer’s not yet there! However, Mehndiratta did touch upon Cadence’s solution that is built upon decades of experience in this area and a strong eco-system made up of partners, third-party providers and foundries. Virtuoso, he added, is the most complete eco-system for designing ICs; not only with its inherent flow, but also because of its linkages to multiple tools inside and outside of Cadence.

“For many years, we have provided a consistent front-to-back flow, and over that time we have learned much about what customers need to do their designs efficiently. It is that knowledge base that we leveraged to accelerate productivity with 6.1 release couple of years back,” he added.

If that is the case, why has it taken so long for a first modern-era mixed-signal implementation solution to be in place?

He referred to Cadence’s next generation Virtuoso 6.1 introduced in November 2006, said to be the first modern, and most complete custom design solution released natively on the OA database. Productivity benefits are significant. RFIC Solutions Inc., a third-party intellectual property and design service provider, is said to have increased productivity two-fold by adopting the Cadence Virtuoso custom design platform.

Likewise, INSIDE Contactless, a fabless company and leader in contactless technology providing high-performance chipsets for secure, fast and reliable transactions with electronic identification, saved 20 percent in development time by adopting Cadence Virtuoso UltraSim Full-Chip Simulator, a component of Virtuoso Multi-Mode Simulation with a high-performance digital-solver technology, for the verification of its current and next-generation contactless and Near Field Communication (NFC) system-on-chip (SoC) designs.

He noted: “Specifically, mixed-signal design is evolutionary, not revolutionary. The concept of mixed-signal design isn’t new. People have been designing in this manner for 15+ years. What is new is the more holistic approach being taken by designers developing mixed-signal circuits. The once clear lines between analog and digital design are blurring, and now the idea of “mixed-signal” is being architected in right from the beginning.

“That is why Cadence’s AMS Designer covers transistor to system level design with a single simulation solution for complete verification. It is why Cadence has combined the power of its leading implementation platforms (Virtuoso and Encounter) to handle the implementation of mixed-signal designs.”

Given that Synopsys’ Galaxy Custom Designer can provide a unified solution for custom and digital designs, thereby enhancing designer efficiency, how will it change/affect designing, and the EDA landscape?

Mehndiratta pointed out that Cadence had defined a unified solution long ago. “Our industry leadership in this area, and Synopsys mimicking of that solution are testaments of Cadence’s vision. Competition is good for all industries, the end-customer usually benefits. You can count on Cadence to not only remain competitive, but also retain our industry leadership in custom/mixed-signal design.”

Importance of open architecture
Let us also look at the importance of open architecture that natively supports interoperable PDKs.

Cadence also believes in open architectures. Its Design Framework II was built as an open architecture, and that’s the reason, why there are many companies that have connected (30+) to form a larger ecosystem. Whereas, the Industry Standard Framework has been tried and failed, the company maintains.

Mehndiratta said: The reason it was a failure is the same as interoperable PDKs. Building frameworks and PDKs that are based on a “lowest common denominator” principle do not provide the most optimized design flow. Instead, you are left with systems that try to please everyone and in the end are rejected as bloated beasts retarding the progress of design.”

Finally, how does Cadence propose to address the Galaxy challenge?

As expected, Cadence hopes to continue to provide customers and partners with a framework in which they can build their tools into the Virtuoso design flow in the most optimized way possible.

Also, by providing its proven and industry standard Pcell technology that takes advantage of the key features in Cadence’s design flow, thereby allowing for fast and productive design today and in the future.