EDA Tech Forum 2010: Nanoscale regime and social product innovation!

This a continuation of my coverage of the Mentor Graphics’ EDA Tech Forum 2010.

Here, I shall discuss the main points of the two keynotes by Dr. Kota Murali, lead scientist & program manager of nanotech, IBM India, and Manjunatha Hebbar, VP & Head – Strategic Services, HCL Technologies Ltd — my good friend and fellow board member at the Indian Microelectronics Academy (IMA).

Nanotech for a smarter planet

Dr. Kota Murali, lead scientist & program manager of nanotech, IBM India @ EDA Tech Forum 2010.

Dr. Kota Murali, lead scientist & program manager of nanotech, IBM India, presented on nanotech for a smarter planet. The motivation for nanotech at IBM has been — since IT has grown as devices have shrunk. Now, we have reached the nanoscale level. The challenge is: how do we take new technologies to markets?

He briefly touched upon IBM’s latest generation processor, the Power7, built on 45nm. The next generation Power8 processors are supposed to be built on 22nm/32nm.

He said that physical and chemical properties of materials depend on the size. Hence, it is important to use nano and quantum scale properties for next generation devices. There is this classical scaling reality — to maintain generational performance gains, supply voltage is not scaled ideally, leading to major power issues.

In the future, innovation, scaling and power will drive performance. Power will play a critical role in developing next-generation products.

On the novel high-K metal gate (HKMG) devices, these gates are already four monolayers thick. We need HKMG since it significantly reduces gate leakage and chips consume lesser power. Also, it allows equivalent oxide thickness. The shrinking of transistor dimensions can continue unhindered.

Dr. Murali highlighted chemical quantization — which allows changes in device parameters, as well as energy quantization — which leads to changes in the fundamental current-voltage characteristics of a transistor. A material’s resistance can also change in the nanoscale regime.

GIDL or gate-induced drain leakage is quite relevant to low power devices. GIDL leakage currents are becoming prohibitively high. While HKMG has solved the tunnelling problem, the GIDL issue still remains. Rotating the conventional wafer from <110> to <100> reduces the GIDL by an order of magnitude.

Next, what’s the alternative to CMOS devices? These could be 3D transistors with better gate control at 15nm and beyond as well as carbon nanotubes. I checked the Web: carbon nanotubes are molecular-scale tubes of graphitic carbon with outstanding properties. They are among the stiffest and strongest fibres known, and have remarkable electronic properties and many other unique characteristics. Excellent!

Finally, how do you pattern all of these devices? Computational lithography enables density scaling. Challenges include pattern optimization tool, code parallelization, HPC and optics.

Spin electronics could be the next evolution — leading to spintronics devices at nanoscale.  Here, IBM’s Giant Magnetoresistive Head, which has been a giant leap for IBM Research, comes into play.

Social product innovation

Manjunatha Hebbar, VP & Head - Strategic Services, HCL Technologies makes a point!

In his keynote, Manjunatha Hebbar of HCL Technologies stressed that innovation is required at every level across the entire value chain. A compelling alternative would be the social product innovation, or democratization of product innovation.

Benefits of social product innovation are manifold. The prime ones are —
* right product for the right market at the right time at the right price;
* lowest direct cost; sharing of risk and reward;
* real-time on demand access to resources; and
* organic transformation with the market.

He cited the example of Apple’s iPhone, which was launched during the peak of recession. The rest is history, as this smartphone went on to change the dymanics of the mobile phone market!

Hebbar highlighted that the society itself has core values of social product innovation. The core purpose — help everyone have their lives! The focus should be on process innovation and prodct innovation, leading to business innovation.

Today, everyone is on the cloud, mobile, connected and reading everyone. Creative commons is the most accepted license model today. Co-creation is always welcome.

Xilinx to build next-gen FPGAs on 28nm high-k metal gate

Xilinx intros world’s first ultra-high-end FPGA based on 28nm high-k metal gate.

Xilinx Inc. has announced the foundation for a next-generation of Xilinx programmable platforms that will give system designers FPGAs that consume half the power at twice the capacity than previously possible for addressing the Programmable Imperative.

Xilinx’s architecture for next-generation FPGA products will be built on 28nm high-k metal gate (HKMG), high-performance, low-power process at TSMC and Samsung.

According to Suresh  Menon, vice president, product development, Programmable Platforms Development, features of the next-generation FPGAs include:

* Reducing total power consumption enables customers to meet system integration and high-performance targets within their power budgets.
* Scalable unified architecture reduces customers’ investment developing and deploying products.
* Xilinx maximizes the value of 28nm with high-performance, low-power process to accelerate platforms for addressing the programmable imperative.

He highlighted some industry challenges. These include the decline ASICs — with development costs, risk and complexity, and time to market being 2x per node, leading to ASIC starts being 50 percent less per node and the ASIC business at -5 percent per year. The ASSP business model is also challenged. While it has grown at 22 percent CAGR from 2004-2009, the operating margins have declined by 27 percent, thus making tier 2 unsustainable.

Menon cited some examples addressing the programmable imperative — wireless communications, wired communications, industrial scientific and medical (ISM), automotive, consumer, and aerospace and defense.

Lower power initiatives are universal. The challenge is to lower the total power consumption, This has to be achieved without giving up on performance or differentiation. Some examples include: green base stations to reduce carbon footprint, eco-friendly server complexes and communication hubs, automotive power restricted environment, and size, weight, and power requirements in defense.

Consumer demand is also driving network bandwidth. A challenge would be enable 1Terabit switch fabric and 400+Gbps line cards. This could been addressed by providing support for 1+Tbps full-duplex bandwidth for high-end switch fabric, enabling high-performance, non-blocking capability with flexibility to integrate QoS security, etc., and extending support for 40G, 100G, 200G, and 400G line cards.

Menon said, “We are delivering lower power through technology innovation, enabling the lowest power, high performance FPGA.”  This is being done as follows:

* Reduce static power consumption by 50 percent.
– 28nm high-K metal gate high-performance, low power process reduces static power compared to 28nm high performance process.
* Lower dynamic power consumption using architectural innovations.
– Transistor choice and multi-gate oxide techniques reduce dynamic power consumption despite trends.
* Enable additional 20 percent power reduction using advanced tool innovations.
– Clock gating technology.
– Fifth generation partial reconfiguration.