Is enough being done for Indian industry-academia collaboration in VLSI education?
Do you, as a semiconductor/VLSI/EDA company, run university or educational programs for colleges and institutes? Am sure, you do!
Well, are you providing these various colleges and institutes with the latest tools and EDA software? Perhaps, yes! So, do you regularly check whether your tool is being used properly, or at all? What do you do if the tool remains unopened or unused? Okay, before all of that, are you even guiding the faculty and students to tackle real world problems associated with chip design?
Do the students (and the faculty) know the intricacies of 22nm, 32nm, 45nm, and so on? Are you able to assist students in taping out? Right, is the syllabus taught in all of these colleges good enough to produce the kind of talent and skills that the semiconductor/VLSI industry requires currently, and in the future? Is everything being taught, the latest?
As they say — it takes two to tango… and, it takes two hands to clap! To the Indian academia — how many among you are “really” serious about being trained on a regular basis by the semicon/VLSI/EDA industry? What have you all done about it so far, all of these years? How many colleges and institutes among you (and do you) regularly put up or raise your hand to the industry and say — we lack the knowledge in a particular area and need training – please help us!
The question is: what are you, as a semicon/VLSI/EDA company, doing about training the various faculty and the students in various colleges and institutions across India? Do you have a proper program in place for this activity? Well, is enough being done regarding the industry-academia collaboration in VLSI education in India? What more needs to be done?
Are you, as a college or institute teaching VLSI, happy with the quality of talent coming out? Are you really satisfied with the quality of B.Tech/M.Tech projects? Do you seek industry’s help regarding training on a regular basis? What steps do you take to reach out to them? And, what are you doing about it all? Do you take that initiative seriously?
For that matter, are there easy-to-use systems that enable effective and industry-relevant education? Are those being made use of properly? Can entry barriers be lowered for students and faculty so they can explore an IP idea that has business potential? How many of the colleges have done this? I know of some folks trying to develop such solutions, but that’s a separate story for another day!
Coming back on track, apparently, some semicon companies and few well known Indian institutes are really exceeding themselves, but the same story does not hold true everywhere. Why is it so?
There could be a variety of reasons, and not all are listed here. Is it a lack of initiative on part of the industry and the institutes? Don’t they even talk to each other? Are institutes not able to approach semicon companies and vice versa? Or, is it the locations of the institutes themselves? Is it that not all institutes are concerned about teaching their students how to solve real world chip design problems?
An industry friend had once remarked: As of the last three-four years, students from the Eastern part of India have no clear pathway that they can pursue to get into VLSI design. The reasons are — there are no training institutes in the East, which can teach Synopsys or Cadence tools or even the basics of Xilinx FPGA design.
A very interesting panel discussion titled Forging win-win industry-academia collaboration in VLSI education was held during the Cadence CDNLive India University conference.
Moderated by Dr. C.P. Ravikumar, technical director, University Relations, TI India, the panelists were Dr Ajit Kumar Panda from NIST Behrampur, K Krishna Moorthy, MD, National Semiconductor India, Dr K. Radhakrishna Rao, head, analog training, TI. India and R. Parthasarathy, MD, CADD Centre.
I have already covered Dr. Ravikumar’s remarks separately.
Let’s see what the other panelists have to say about all of this, and whether they have answers to all of the questions or problems. Well, this is another long post, so please bear with me! 😉 Read more…
Forging win-win industry-academia collaboration in VLSI education
Despite all the talk of semicon/VLSI going around in India, is the correct curriculum really being taught in the various institutes? Is the academia able to prepare students to be better equipped to tackle today’s world’s problems? Does the student have sufficient skills that the Indian (and global) semicon industry recruiters are looking for? Is the student, and the academia semiconductor-industry ready sufficiently?
There was a lively panel discussion titled: Forging win-win industry-academia collaboration in VLSI education during the post lunch session of CDNLive India University conference.
I remember last year’s CDNLive India panel discussion quite clearly! There was an entertaining session on how to prepare the students to be semiconductor industry read. It remains a top read till date!
This year’s panel discussion was moderated by Dr. C.P. Ravikumar, technical director, University Relations, Texas Instruments India.
The panelists were:
* Prof Ajit Kumar Panda, NIST Behrampur, Orissa.
* K Krishna Moorthy, MD, National Semiconductor India
* Dr K. Radhakrishna Rao, head, analog training, TI.
* R. Parthasarathy, managing director, CADD Centre.
Starting the discussion, Dr. Ravikumar said that the semicon industry is currently seeing fast paced growth. New knowledge is getting added every year. The semicon industry has been present in India for over 25 years now, and counting.
There is a varied expectations from the academia in India. For instance, should they teach fundamentals or skills? Do they have silicon experience, or can the institute bring this about on its own? What is important — going up or down the abstraction level?
Or, should VLSI education be introduced at the graduate level or should it be in the Masters leel? There are several gaps in the curriculum itself. What can the industry do about those gaps?
Dr. Ravikumar said: “TI is celebrating 25 years. The kinds of problems TI is working on today are vastly different from the times when it had started in India. Today, it is doing large SoCs. The industry has hige expectations from the academia.
People, he added. seem to have diverse opinion on VLSI. Even at abstraction levels, we can talk about power, circuit design, larger blocks, etc. You will likely hear different sort of viewpoints depending on who you are talking to.
He said: “A lot of effort is being put into the formation of new M Tech programs in VLSI across various institutes. Wheher the students passing out from these institutes will find employment in the Indian semiconductor industry- is also a point of debate. Again, I’ve seen VLSI being talked about in the graduate level as well.”
Since there were four panelists, I shall add their views in a separate post. Stay tuned, folks! 😉
India's teaching community contemplates SoC design
The VLSI Society of India recently organized a two-day faculty development workshop on SoC design, — Train-the-Trainer program — on Oct. 30-31, 2010, at the Texas Instruments India office, in co-operation with PragaTI (TI India Technical University) and Visweswaraya Technological University (VTU).
I am highly obliged and very grateful to the VLSI Society of India and Dr. C.P. Ravikumar, technical director, University Relations, Texas Instruments India, for extending an invitation. Here is a report on the workshop, which the VSI Secretariat and Dr. Ravikumar have been most kind to share.
System-on-chip (SoC) refers to the technological revolution, which allows semiconductor manufacturers to integrate electronic systems on the same chip. System-on-board, which has been the conventional implementation of electronic systems, uses semiconductor chips soldered onto printed circuit boards (PCBs) to realize system functionality.
Systems typically include sensors, analog frontend, digital processors, memories and peripherals. Thanks to the advances in VLSI technology, these sub-systems can be integrated on the same chip, reducing the footprint, cutting down the cost, improving the performance and power efficiency.
While the industry has adopted SoC design for many years, the academic community around the world (India not being an exception) has not caught up with the state-of-the-art. Electrical/electronics engineering departments continue to teach a course on VLSI design, where the level of design abstraction is device-level, transistor-level, or gate-level.
Register-transfer-level (RTL) design using hardware description languages is taught in some Masters’ programs, but colleges often do not have the lab infrastructure to carry out large design projects; very few Indian universities have tie-ups with foundry services to get samples. A semester is too short a time to complete a large project.
The complexity of modern-day design flow is not easy to impart in a single undergraduate course. Masters’ programs are particularly relevant in VLSI, but the M.Tech programs in the country languish due to several reasons.
Ground realities
“M.Tech programs do not attract top students who are highly motivated,” said a professor who attended the two-day faculty development program organized by VLSI Society of India. “Almost all undergraduate programs today have a course on VLSI technology and design. But since we get students from different backgrounds, they do not have the pre-requisites. So, a course on VLSI design at M.Tech level will have a significant overlap with an undergraduate course on VLSI design.”
“Faculty members need training,” said another teacher. “When a new course is introduced, significant time is needed for preparation. Prescribed textbooks for a new course are often not available. Internet search for course materials often returns too much material and it is hard to decide what to use. Colleges that have autonomy can decide their own curriculum, but in a university setup, the faculty face a major challenge. We are evaluated on how well our students fare in the exams. Yet, our students have to face an exam made by a central committee.”
“Having a common exam poses many problems in setting up a relevant question paper. The format of the question paper is fixed. The students get a choice of answering five questions from a set of eight. Due to the common nature of the question paper, the questions tend to demand descriptive answers.”
Faculty development workshop on SoC design
About 30 faculty members interested in system-on-chip design took part in the faculty development workshop. The attendees came from about 25 different colleges from VTU, VIT University, and Anna University. The workshop was conducted in co-operation with the Viswesaraya Technological University (VTU) and sponsored by Texas Instruments, India.
The premise for the workshop was that a course on SoC design is required at the Masters’ level, since industrial practice has clearly moved in that direction. The RTL-to-layout flow, which continues to be relevant for IPs that constitute an SoC, aspects of SoC design, which relies on IP integration, are not covered in any course.
The workshop provided a forum for industry-academia interaction. Several professionals from the industry took part in the workshop and answered questions from the faculty members. Read more…
Some thoughts on VLSI manufacturing in India
VLSI manufacturing: The government of India has to give appropriate incentives to this industry and suitably phase these to allow an ecosystem to build up. The fabless model is fine for companies to transact their business. But, India needs to have this technology or some semblance of it to start with or else it would never be able to count herself amongst the leading nations of the world. How can we achieve that?
a) One of the quickest ways to get started is to create an organization (with equity wholly or partly owned by the government of India) with the charter that that company invest in/fractionally own some of the leading semiconductor manufacturing facilities in Taiwan. TSMC may be very difficult to own even modest percentages, but simultaneously buying reasonable stakes in UMC, Chartered Semiconductor, the IBM multi-platform consortium may be possible with (my guess) at under $1 billion that gives adequate leverage. This organization then makes available fab capacity (that is available to them now due to their fractional ownership) to fabless product companies with intended product sales in India.
b) Repeat the above for packaging, assembly, and VLSI test operations. (The challenges are less here though, but these are just as important elements of the ecosystem).
c) With this, India will “own” leading edge VLSI technology although in a circuitous manner, but given that we missed the boat by over 20 years I think this is a reasonably low cost but effective way to get a starting foothold.
d) Next, and in parallel, the government ought to give incentives to companies to create semiconductor manufacturing capacities on Indian soil but buying re-furbished and lower cost equipment at previous generation technology nodes.
Some policies are required here that allow easy transport back-and-forth of sub-assemblies for repair and replacement.
e) Eventually, the organization(s) in (d) above will “catch” up with those in (a) above. There will need to be phased modification of the incentives, reducing some, changing some such that over a six-seven year period all incentives can go away and the eco-system will be self sustaining.
f) Well, not quite, we will also need to address (i) the semiconductor manufacturing, assembly, test equipment manufacturing and (ii) the semiconductor manufacturing raw materials (silicon wafers, silicon grade pure chemicals, etc etc). The focus to these technologies have to be phased to the decade after the steps outlined in (a) to (d) have yielded some measurable results.
Friends, please feel free to share your thoughts, comments, etc., and add value.
VLSID 2010 to focus on affordable technologies for emerging markets
The 23rd International Conference on VLSI Design and the 9th International Conference on Embedded Systems (VLSID 2010) will be held at the NIMHANS Convention Center in Bangalore from January 3 to 7, 2010.
Over 700 delegates from India and abroad are likely to participate in this premier VLSI conference. It provides a forum for researchers and designers to present and discuss various aspects of VLSI design, electronic design automation (EDA), enabling technologies and embedded systems.
The first two days of the conference will feature full day tutorials by worldwide experts and the main technical program of the conference will be held on the following three days.
Dr. Biswadip (Bobby) Mitra, President & Managing Director, Texas Instruments India will inaugurate the conference on January 5, 2010.
I was in conversation with Dr. Mahesh Mehendale, General Co-chair VLSID 2010 and Texas Instruments Fellow & Director, Center of Excellence for Digital Video, Texas Instruments India, and Dr. Srivaths Ravi, General Co-Chair VLSID 2010 and DFT Lead at Texas Instruments India.
According to Dr. Mehendale, this year’s conference has a theme “Affordable Technology for Emerging Markets”. The intent is to focus on what it takes to build low-cost chips and systems for emerging markets and applications. Some of the sessions revolve around this theme.
“We have several eminent keynote speakers this year. To name some of them, we have the father of Digital Micromirror Device (DMD) — Dr. Larry J Hornbeck, Texas Instruments Fellow and inventor, the chip that became the basis for Digital Light Processing (DLP) technology, visiting us this year. He will talk about DMD and DLP. Dr. Walden C Rhines, Chairman & CEO, Mentor Graphics, is another keynote speaker. He will be speaking on ‘Delivering 10X Design Improvements’.”
In terms of coverage, across keynotes, theme sessions, panel and embedded tutorials, the conference has a very high profile program.
On January 3-4, there will be mainly tutorials on these two days. The topics will cover the various aspects of VLSI design. It will also look at testing as an important component.
Dr. Mehendale said: “We are taking the conference to the desktops of the professionals and people who may not be able to attend in person! On days 3, 4, 5 (i.e., the main conference program), we will be webcasting three of the four sessions. We are considering recording the fourth session and make it available for relay later.