Excerpts from Future Horizons' IEF 2009 — II

Presenting excerpts of some more key presentations made on day 1 and 2, resepectively, at the recently held International Electronics Forum 2009 (IEF 2009), in Geneva, Switzerland, from Sept. 30-Oct. 2, which was held under the auspices of the Geneva Chancellerie D’Etat & Istitut Carnot CEA LETI.

May I also take this opportunity to thank Malcolm Penn, chairman and CEO, Future Horizons.

“ICT: Key For Global Competitiveness” — Enrico Villa, chairman, CATRINE

Enrico heads up the Cluster for Application and Technology Research In Europe on NanoElectronics (CATRINE) and through his organisation Europe is preparing for our future with development projects in nanotechnology, microelectronics, photonics, biotechnology and advanced materials.

Electronic and information systems are worth $87 trillion and growing, which is about 10 percent of global GDP. Such systems have penetrated all aspects of life, created millions of jobs and has been a motor of productivity growth.

Microelectronics is a key enabling technology for electronics and ICT, and as a consequence the semiconductor market grows at twice this GDP. The role of electronics will increase in the future and will have an impact in society due to its use in healthcare, aids for an aging population, easing transportation bottlenecks and lowering energy costs.

To meet these targets electronics and ICT must be affordable to the population at large – meaning that semiconductors must meet the trend of doubling performance every two years, reduce price per function by 40 percent per year and aim for R&D nearly 20 percent of sales.

In an example given public lighting is 13 percent of energy costs – a change to semiconductor LEDs can save a third of this energy. Enrico sees moving from ideas to products is one area where Europe is weak, but thankfully projects Jessi/Eureka/Catrine/Medea+ are bringing together cooperation between European players.

This has enabled European companies and universities to work together and create critical masses to make global products. This is born out in the fact that Europe has several global-sized semiconductor companies and two European equipment-material suppliers that are world leaders.

“Raising The Bar On Semiconductor R&D Management, Execution & ROI” — Ronald Collett, CEO, Numetrics Management Systems

Working with the company PRTM Ron is tasked to raise the management competence within the semiconductor industry so companies can compete in the global arena. The semiconductor industry is going through a profound change with the vertically chip companies disintegrating and outsourcing their manufacture. Headcount has fallen, there are fewer start-ups and everybody is cutting costs.

Companies that will survive are those with well differentiated products and superior product development ability. PRTM has produced an integrated framework of product development capabilities, which compares company actual performance against industry best practice and timescales.

It is a fact that 60 percent of semiconductor projects slip in time by at least one quarter and 16 percent slip by more than one year. The system allows ‘fact-based planning and decision making’ and allows management to get no surprise shortfalls in revenue or margin.

At a detailed level, the engineer can make a fact-based project cost estimation and can reliably make staffing requirements and schedules. It allows ‘what-if’ project analyses and calculates risk. The immediate impact is usually a reduction of projects, but a better time-to-market and ROI. An industry shakeout is inevitable and demands will overwhelm all, but the best.

“Building Complex Embedded Software Applications On Leading Edge Silicon” — Martin Orrell, General Manager, Multimedia Technologies, The Technology Partnership

TTP is an independent product development company involved in a wide range of products including embedded systems in medical devices, PC peripherals, MP3 players and automotive, industrial and traffic control.

Martin’s view is that one of the difficulties in embedded design is to recognise that the hardware and software boundaries tend to blur. Using software rather than hardware has its advantages, particularly where the standards and specifications have not firmed up, but software often costs more than the customer planned.

Costs can be saved by the re-use of silicon and software IP, the starting platform and roadmap, trimming the specification and through innovation. TTP has a wide range of experience and can often view a customer project from a different perspective and Martin gave a number of good examples of case studies where this was the case.

To finalise, two tips were given to product developers: More complex software does not mean higher project costs and silicon targeted for a different market can enable innovative opportunities in your own market.

Mentor Graphics: DFM is where all the value is!

As promised, here is the concluding part of my discussion with Joseph Sawicki, vice president & GM, Design to Silicon Division, Mentor Graphics.

We went over the design for manufacturing (DFM) challenges and how yield can be improved. He also touched upon the design challenges in 45nm and 32nm, respectively.

Given that the semiconductor industry does speak a lot about DFM, what steps are being taken to improve on the overall yield?

According to Sawicki, in the VLSI microchip era, yields started at 60-70 percent, and so DFM wasn’t required. However, in the nanochip era, DFM is where all the value is. [VLSI Research.]

Joseph Sawicki, vice president & GM, Design to Silicon Division, Mentor GraphicsHe added that at smaller geometries, manufacturing variability has a much greater impact on timing, power dissipation, and signal integrity. Traditional guardbanding is no longer sufficient to guarantee competitive performance at acceptable yields, and excessive design margins erase the advantages sought by going to the next node in the first place.

Moving to advanced technologies without dealing effectively with manufacturing variability can actually put a design at a competitive disadvantage due to low parametric yield.

“Successful IC implementation requires a detailed understanding of how variability affects both functional and parametric yield. Customers need a manufacturing-aware engineering approach that extends across the entire physical implementation life cycle, starting with cell library development and extending through place and route, physical verification, layout optimization, mask preparation, testing, and failure analysis.

“They need a design flow that helps them “co-optimize” for both performance and yield simultaneously, based on accurate models of manufacturing process variability. The ability to do this quickly and effectively can give IC designers a powerful competitive advantage,” Sawicki said.

There is no silver bullet! It takes a broad-based, well-integrated approach to have a significant and consistent impact on manufacturability.

According to him, Mentor Graphics provides a complete manufacturing-aware design-to-silicon solution addressing random particle effects, small-scale device and interconnect interactions, lithographic distortions and process window variations, and thickness variations resulting from chemical-mechanical polishing (CMP) and variable film deposition and etch rates.

“Our tools incorporate comprehensive, highly-accurate models that have been tuned and verified for specific manufacturing environments, and address every stage of the digital IC implementation life cycle,” he added.

So, how is Mentor handling 45nm and 32nm design challenges?

Sawicki added: “Advanced process nodes present challenges at every stage of IC implementation, from place-and-route, through physical verification, layout enhancement, testing and yield analysis. Mentor has a complete design-to-silicon flow that addresses the critical challenges of IC implementation at every stage.”

Mentor on EDA trends and solar/PV

This is a continuation of my recent discussion with Joseph Sawicki, vice president & GM, Design to Silicon Division, Mentor Graphics.

There have been whispers that the EDA industry has been presently lagging behind semiconductors and is in the catch-up mode. “That’s a matter of perspective. There are definitely unsolved challenges at 32nm and 22nm, but the reality is that we are still in the technology development stage,” he says.

For EDA tools that address implementation and manufacturing issues (i.e., Mentor design-to-silicon products), there are dependencies that cannot be fully resolved until the process technology has stabilized. Mentor Graphics is laying the groundwork for those challenges and working in concert with the process technology leaders to ensure that our products address all issues and are production-worthy before the process technology goes mainstream.

On the other hand, although Mentor’s products are fully-qualified for 45nm, there have only been a handful of tapeouts at that node, so for the majority of customers, we are ahead of the curve.

On ESL and DFM as growth drivers
ESL and DFM are said to be the new growth drivers. Sawicki adds: “As Wally Rhines has said in his public presentations, system level design and IC implementation are the stages of development where there are the most challenges, and therefore the most opportunities. To continue the traditional grow spiral that the electronic industry has enjoyed as a result of device scaling, we need more sophisticated EDA solutions to deal with both of these challenges.”

ESL is responding to the growth of design complexity and the need for earlier and more thorough design verification, including low power characteristics, and software integration.

The Design-to-Silicon division is addressing the issues of IC implementation which result not only from the increase in design complexity and devices sizes, but also from increasing sensitivity of the manufacturing process to physical design decisions, a phenomenon often referred to as “manufacturing variability.”

Although the term “Design-For-Manufacturing” reflects the need to consider manufacturability in design and to optimize for both functional and parametric yield, it is important to emphasize that DFM is not simply an additional tool or discrete step in the design process, but rather an integration of manufacturing process information throughout the IC implementation flow.

With single threading, we can no longer handle designs over 100 million gates. Of course, at 45nm, you can do a 100mn gates. That rewriting process is another issue that is also slowing out. It would be interesting to see how is Mentor handling this.

According to Sawicki, Mentor has incorporated sophisticated multi-threading and multi-processing technologies into all of its performance-sensitive applications, from place-and-route, through physical verification, resolution enhancement and testing.

He says, “Our tools have a track record of impressive and consistent and performance and scalability improvements, which is why we continue to lead the industry in performance.”

In addition to merely adding multi-threading and support for multi-core processors, Calibre products have a robust workflow management environment that automatically distributes the processing workload in the most efficient manner across any number of available clustered computing nodes.

Mentor’s Olympus-SoC place-and-route is inherently scalable due to its advanced architecture which includes an extremely efficient graph representation for timing information, and a very concise memory footprint. In addition, all the engines within Olympus-SoC can take advantage of multi-threaded and multi-core processors for high performance. These features enable Olympus-SoC to handle 100M+ gates designs in flat mode without excessive turnaround time.

Mentor’s ATPG tools are also designed to operate in multiprocessing mode over the multiple computing platforms to reduce test pattern generation time. In addition, Mentor test pattern compression technology reduces test pattern volume and test time, making it feasible to fully test 100M gate devices and maintain product quality without an explosion in test cost.

With EDA is starting to move up to the system level, will this make EDA less dependent on the semiconductor world?

Sawicki agrees that there are challenges at both the front end and back end of the electronic products design and manufacturing life cycle. Both of these opportunities are growing. In addition, developments like multi-level (3D) die packaging, through-silicon via (TSV) structures and other non-traditional techniques for device scaling are pushing system and silicon design issues closer together.

Reaching the 22nm node will require highly compute intensive EDA techniques for physical design to compensate for limitations in the manufacturing process. Beyond that, we could see a major shift to new materials and manufacturing techniques that would open new green fields for EDA in the IC implementation flow.

EDA going forward
How does Mentor see the EDA industry evolving, going forward?

Sawicki adds: “There are three key trends to watch. Firstly, for design to remain affordable at the leading edge, we need to enable radical increases in productivity. Electronic System Level (ESL) design is the key here, allowing designers to move to a new level of abstraction for both design and verification.

“Secondly, the challenges of manufacturing a well-yielding and reliable device as we move to 22nm will require a far more sophisticated physical implementation environment—one that accounts for physical effects in the design loop, and accounts for manufacturing variability in it’s optimization routines.

“Finally, the manufacturing challenges also open significant opportunity for EDA in the manufacturing space. A great example of this is the September 17, 2008 announcement we did with IBM on a joint development program to enable manufacturing at the 22nm node.”

Finally, given the roles already defined by Magma and Synopsys in solar, is there an opportunity for EDA in solar/PV?

According to Sawicki, as the photovoltaic devices have very simple and regular structures, most of the opportunity for EDA is not in logic design tools, but in material science, transistor-level device modeling, and manufacturing efficiencies with a focus on conversion efficiency and manufacturing cost reduction.

EDA’s role in solar will be in the newer areas related to Design-for-Manufacturing and other manufacturing optimizations, he concludes.

Our last discussion on DFM will follow in a later blog post!

Despite EDA challenges, Mentor keeps faith on India

Great! All of these EDA firms, despite their current financial woes, remain strong and bullish on India! Mentor Graphics is no exception in this case!

It is well documented that the global EDA industry, along with the global semiconductor industry, has not had a smooth ride this year. However, this situation has only made both the industries work harder toward restoring some recovery.

Thanks to Veeresh Shetty, a dear friend, and Marcom Manager-Pacrim South, Mentor Graphics, I had the pleasure of meeting up with Joseph Sawicki, vice president & GM, Design to Silicon Division, Mentor Graphics Corp., during the recently held EDA Tech Forum in Bangalore.

We discussed a range of issues, such as the state of the EDA industry, Mentor’s focus on India, and low-power design challenges. I did not discuss the proposed acquisition of Mentor by Cadence, as I feel it is no point in going over what was never on the cards, at least, for now.

According to Sawicki, Mentor Graphics is very optimistic about semiconductors and electronics, especially in India. “The EDA industry is currently having a pretty challenging environment. The recession in 2002 was the deepest in its history,” he says.

“We (the EDA industry) haven’t had the growth rates we would like. However, we have done better. We have re-invented Mentor,” adds Sawicki. “We have now invested more in back-and-route ICs, which is about 40 percent of our revenue. Our product portfolio is the youngest within the company.” He adds that the recession has been more in semiconductors. However, take out memory, and the scenario changes.

The drive of the semiconductor industry toward smaller and smaller features sizes requires more sophisticated correction methods to guarantee the final tolerances for the etched features in both wafer manufacturing and mask making.

Flat growth likely for EDA
Commenting on EDA industry’s growth, Sawicki, adds that growth will be flat in 2008. Interestingly, the growth rate for EDA was 10 percent during the last two years. He notes: “EDA always does best when it delivers new technology. There are two reasons. One, on the manufacturing side of things. The extra results will be completely delivered by the software.”

The other reason is that the aspects of manufacturing power and manageability will assume great importance. “Finally, the ESL space also provides the potential for growth. It also brings out a whole new design capability,” he notes.

Given the global semiconductor scenario, Mentor is also looking at other markets outside semiconductors, especially automotive. Sawicki adds that this quarter, 20 percent of Mentor’s business has been from the automotive segment.

There have been several global initiatives aimed at consolidation in the recent past. Sawicki says: “Consolidation should not be looked at as a goal. We also do acquisitions in the technology space. It augments a strong position.”

So what are some of the other challenges facing the industry? Sawicki lists those as the economics of the industry itself, especially the design and verification costs.

On low power design, Sawicki agrees that there has been a transition of electronics from the US to Asia. “You have got to handle far lower power downward. We can reduce leakage current by 20-30 percent. Looking forward, how do you tie in ESL with physical design? When doing ESL, you can do architectural exploration. I will have my ESL to drive the place-and-route tool. I can get fast execution as well as low leakage power.”

He advises that India has the ability to go beyond the innovation that has been happening.

Mentor in India
Mentor Graphics has three sites in India. It has R&D centers in Hyderabad and Noida, near New Delhi, and a sales and support office in Bangalore. The Hyderabad R&D center handles system design, while the Noida R&D center takes care of the front-end side, such as functional verification products.

Raghu Panicker, sales director, India, Mentor Graphics, says that the company has been very bullish on India. “We do not see any lull anywhere. Lot of design starts are happening here, in India,” he adds.

I will continue my conversation with Joseph Sawicki in the next blog!