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EDA Tech Forum 2010: Nanoscale regime and social product innovation!
Here, I shall discuss the main points of the two keynotes by Dr. Kota Murali, lead scientist & program manager of nanotech, IBM India, and Manjunatha Hebbar, VP & Head – Strategic Services, HCL Technologies Ltd — my good friend and fellow board member at the Indian Microelectronics Academy (IMA).
Nanotech for a smarter planet
Dr. Kota Murali, lead scientist & program manager of nanotech, IBM India @ EDA Tech Forum 2010.
Dr. Kota Murali, lead scientist & program manager of nanotech, IBM India, presented on nanotech for a smarter planet. The motivation for nanotech at IBM has been — since IT has grown as devices have shrunk. Now, we have reached the nanoscale level. The challenge is: how do we take new technologies to markets?
He briefly touched upon IBM’s latest generation processor, the Power7, built on 45nm. The next generation Power8 processors are supposed to be built on 22nm/32nm.
He said that physical and chemical properties of materials depend on the size. Hence, it is important to use nano and quantum scale properties for next generation devices. There is this classical scaling reality — to maintain generational performance gains, supply voltage is not scaled ideally, leading to major power issues.
In the future, innovation, scaling and power will drive performance. Power will play a critical role in developing next-generation products.
On the novel high-K metal gate (HKMG) devices, these gates are already four monolayers thick. We need HKMG since it significantly reduces gate leakage and chips consume lesser power. Also, it allows equivalent oxide thickness. The shrinking of transistor dimensions can continue unhindered.
Dr. Murali highlighted chemical quantization — which allows changes in device parameters, as well as energy quantization — which leads to changes in the fundamental current-voltage characteristics of a transistor. A material’s resistance can also change in the nanoscale regime.
GIDL or gate-induced drain leakage is quite relevant to low power devices. GIDL leakage currents are becoming prohibitively high. While HKMG has solved the tunnelling problem, the GIDL issue still remains. Rotating the conventional wafer from <110> to <100> reduces the GIDL by an order of magnitude.
Next, what’s the alternative to CMOS devices? These could be 3D transistors with better gate control at 15nm and beyond as well as carbon nanotubes. I checked the Web: carbon nanotubes are molecular-scale tubes of graphitic carbon with outstanding properties. They are among the stiffest and strongest fibres known, and have remarkable electronic properties and many other unique characteristics. Excellent!
Finally, how do you pattern all of these devices? Computational lithography enables density scaling. Challenges include pattern optimization tool, code parallelization, HPC and optics.
Spin electronics could be the next evolution — leading to spintronics devices at nanoscale. Here, IBM’s Giant Magnetoresistive Head, which has been a giant leap for IBM Research, comes into play.
Social product innovation
Manjunatha Hebbar, VP & Head - Strategic Services, HCL Technologies makes a point!
In his keynote, Manjunatha Hebbar of HCL Technologies stressed that innovation is required at every level across the entire value chain. A compelling alternative would be the social product innovation, or democratization of product innovation.
Benefits of social product innovation are manifold. The prime ones are —
* right product for the right market at the right time at the right price;
* lowest direct cost; sharing of risk and reward;
* real-time on demand access to resources; and
* organic transformation with the market.
He cited the example of Apple’s iPhone, which was launched during the peak of recession. The rest is history, as this smartphone went on to change the dymanics of the mobile phone market!
Hebbar highlighted that the society itself has core values of social product innovation. The core purpose — help everyone have their lives! The focus should be on process innovation and prodct innovation, leading to business innovation.
Today, everyone is on the cloud, mobile, connected and reading everyone. Creative commons is the most accepted license model today. Co-creation is always welcome.
IDF Taiwan: Desktops with Intel Core i7; IBM, Intel ally on Blade servers
There’s more news from IDF, Taiwan, folks! One, Intel is all set to launch high-end desktops powered by the Intel Core i7 processor, next month. This was disclosed by Kirk B. Skaugen, Vice President, Digital Enterprise Group, General Manager, Server Platforms Group, in the Digital Enterprise Keynote: IA = Embedded + Dynamic, during the recently held Intel Developer Forum (IDF).
Intel vPro technology-based business clients: “Piketown” for desktops and “Calpella” for notebooks, will be powered by future Nehalem processors and will provide corporate customers with even more enterprise-focused innovations.
Also, Intel and IBM strengthened their Blade server segment partnership. More of that a bit later!
According to Skaugen, we are in the third stage of the Internet revolution. “The fourth stage is the pervasive Internet. By 2015, there will be 15 billion devices connected to the Internet. The Atom processor has unleashed a new wave of connected devices. However, these devices will need massive infrastructure support as well. Storage will also become a massive area of growth and development,” he added.
IBM Switch specs opened to SSI
According to Skaugen, the best infrastructure is built on infrastructure standards. Citing IDC figures, he said that the Blade market growth will be 37 percent CAGR during 2007-11. The Apac market will grow 78 percent.
IBM and Intel also strengthened their alliance in Blade servers. Mark Wiltse, IBM Systems & Technology Group, said that Blade.org has been created and is focused on solutions collaboration. “We are opening up the IBM Switch specifications to Server Systems Infrastructure (SSI). This will create broader opportunities in Blade. There is broad support for SSI Blade specifications.” IBM will extend the BladeCenter switch specification for blade servers to the SSI on a royalty-free basis.
Commenting on the Nehalem, Skaugen added that it is a next generation microarchitecture, using second generation of virtualization, and there is 3X memory bandwidth support as well. Intel’s Power Boost technology has also been used on the Nehalem.
Skaugen also provided details of next-generation high-end desktops powered by the Intel Core i7 processor, launching next month. These high-end desktops will provide outstanding performance for gaming and content creation applications.
Calpella and Piketown in the offing
He shared that the 2009 Intel vPro technology-based business clients codenamed “Piketown” for desktops and “Calpella” for notebooks will be powered by future Nehalem processors and will provide corporate customers with even more enterprise-focused innovations.
The upcoming Nehalem microarchitecture spans a range of products. First segments will include the Intel Core i7 processor and a variant designed for the efficient performance server segments codenamed “Nehalem-EP.”
A derivative designed for the expandable server market segment (“Nehalem-EX”) as well as other desktop and mobile versions (“Havendale,” “Lynnfield,” “Auburndale” and “Clarksfield”) will be in production beginning in the second half of 2009.
Nehalem’s integrated power gate
Stephen S. Pawlowski, Intel Senior Fellow, highlighted that the Nehalem has an integrated power gate. “We have got the M9 (metal 9) deposited on the silicon to create low-power resistance.” Having power gates means that the idle cores use near zero power.
Several Intel partners also showcased their products at IDF Taiwan. There were 37 new motherboards, while the Nehalem EP was touted as the world’s most adaptable server platform. Skaugen said: “it is energy efficient and designed for virtualization. Also, there is investment protection with FlexMigration.”
32/64GB SSDs on offer
Intel also introduced its range of SSDs, in 2.5-inch form factors, with 32/64GB storage at the IDF.
Citing SSD benefits, he said these included 6X performance increase, 46X power reduction and 75 percent space reduction.
Encouraging developments in 22nm!
Suddenly, but steadily, there seems to be lot of work going on in the 22nm space. This can only be encouraging for the global semiconductor industry.
Savor these! This week, SEMATECH researchers presented trend-setting research results in extending the CMOS logic and memory technologies at the International Symposium on VLSI Technology, System and Applications (VLSI-TSA), which ran from April 21-23, at Hsinchu, Taiwan.
According to SEMATECH, the new materials, processes and concepts discussed in a series of seven research papers describe how current semiconductor technologies can benefit from performance-enhancing features for future scaling needs.
The papers discuss leading-edge research into areas such as high-k/metal gate (HKMG) materials, flash memory, planar and non-planar CMOS technologies, including new finFET designs, which offer additional control on the channel or body of the device by using a controlling gate wrapped around a thin silicon “fin”.
Early this month, Chartered Semiconductor Manufacturing, one of the world’s top dedicated foundries, announced the extension of its joint development collaboration with IBM to include 22nm bulk complementary metal oxide semiconductor (CMOS) technology.
IBM and AMD have also been collaborating on the development of next-generation semiconductor manufacturing technologies since January 2003. In November 2005, the two firms announced an extension of their joint development efforts until 2011, covering 32nm and 22nm process technology generations. Intel has been working on 22nm for quite some time now.
And last July, PULLNANO, a project sponsored by the European Commission within the 6th Framework Program (FP6), reported several important results related to the future-generation 32nm and 22nm CMOS technology platforms, including the realization of a functional CMOS SRAM demonstrator built using 32nm design rules.
PULLNANO also proposed an innovative new architecture that could provide even higher performance at 32nm and 22nm, using the so-called ‘air gap’ technique.
Late last year, I attended a Semiconductor International Webcast, where one of the analysts, Carl Johnson of Research Infrastructure, had said that lot of consolidation was happening within the fab space. Mid-level players are consolidating. The customer base is clearly narrowing.
He said: “The cost of designing some of these leading-edge devices, and getting them to market, and then following it up with another product, if you don’t want to be a one-product guy, is a real challenge. That is limiting the number of players that are going into the mega fabs. So, the field is narrowing in 65nm, and 45nm, and as we get to below 45nm, the field is going to get much, much narrower.”
Perhaps, there will be fewer players after all, in the 22nm space. However, all of the encouraging developments mentioned above augur well for the semiconductor industry.
Pradeep Chakraborty 