No real fun being at DAC or ESC! Seriously!!

The 48th Design Automation Conference (DAC) kicks off in about a month’s time in San Diego, California, USA. I have been flooded with invites. There’s also an Embedded Systems Conference starting tomorrow, in San Jose. However, I will give both of the events a miss! Why? Simply because of one fact! The EDA industry has stopped surprising me! And, so has the embedded systems industry!!

I an very well aware of the changing and ‘challenging’ trends in the global semiconductor industry. I should also add that I do have at least some knowledge of the global EDA industry in 2010 and its expectations for 2011.

I am aware of the fact that product lifecycle management involves reducing the time-to-market cycles for new product introduction. Industry folks have, time and again, apprised me of the fact that there is a need to bridge the gap between software and hardware – and growing the IT and VLSI industries.

Cadence, for instance, will share a new technology that addresses some of the toughest challenges detailed in the EDA360 vision at ESC 2011. For how long will the challenges be met? Synopsys seems to be raking in the dollars, year after year. Mentor, despite its ‘current issues’, has been doing fairly well. So, what’s new over here?

In embedded, it is very well known globally, that India is an emerging leader. Otherwise, there is hardly any electronics or semiconductor related manufacturing happening in India, despite the best efforts of the ISA.

So, why isn’t all of this being viewed as industry growth? Maybe, you have all the answers! I will only try to sound more optimistic, without creating additional pain!

Almost all of the new techniques and technologies to be announced at either conference, will or already have made their way to India. Or, the companies using them are not allowed to speak about them, at best!

Indian semicon industry poised at very interesting juncture: Dr. Pradip Dutta, Synopsys

Dr. Pradip Dutta, corporate VP of Synopsys Inc. and MD of Synopsys (India).

I have known Dr Pradip Dutta, corporate VP of Synopsys Inc. and MD of Synopsys (India), as well as vice chairman, India Semiconductor Association (ISA), and now, chairman designate for 2011, ISA, for close to a decade now. We recently got into an interesting discussion on the Indian semiconductor industry.

Growth of semicon and electronics in India
First, I asked what should be done about the growth of semiconductors and electronics in the Indian eco-system?

Dr. Dutta said: “My view on this subject has been the same for many years now; high-tech electronics has to be a national mission. The defense and the government labs played a major role in promoting this sector in the US; e.g. Sandia National Laboratory, Lawrence Livermore Laboratory, Jet Propulsion Laboratory, NASA etc. DARPA, which is part of US Department of Defense has sponsored phenomenal amount of research in semiconductors and electronics.

“If we now look at countries closer to our part of the world, in Asia, we will see a similar focused effort from the governments. The STARC initiative in Japan, the National SOC program in Taiwan, the 839 program in Korea, the 863 program of Ministry of Science and Technology in China, all catered to a flourishing investment in R&D and innovation in high tech. Our country is poised for it too. We need to encourage start-ups in fabless design, explore manufacturing, foster innovation, create favorable policies for the industry and most certainly develop the talent pool.”

Need for domestic manufacturing
There is a need for domestic manufacturing in high tech electronics. Where are the Indian companies going? According to him, domestic manufacturing in high tech electronics has been flagged as a critical area in the ESDM (Electronic Design and Manufacturing) report that was submitted to the government by the industry in 2010. There is a need for initial funding, both in R&D as well as manufacturing. Duty structures need to be rationalized between import of CBU, SKD, CKD and components.

He added: “We have seen that manufacturing prospers in cluster environment and hence there is a recommendation to promote manufacturing clusters for specific product categories. However, it is safe to say that we have long ways to go in this area.”

Co-operation with international trade bodies
Now, what is the required policy framework and co-operation with international trade bodies?  As per Dr. Dutta, the ISA has been active in forging close working relationships with multiple trade bodies from various parts of the world. “We have signed several MoUs with entities such as HTIA (Israel), ASTSA (Japan), DSP Valley (Belgium), TSIA (Taiwan), Semi (USA), GSA (USA) and UKTI (UK).

“Of course, we need to have a focus and these relationships should be driven by strategy. We have carried several delegations to these countries and hosted bi-lateral visits as well. These visits provide an opportunity for our member companies to have direct B2B opportunities.

“We learn valuable best practices from other entities and try and implement in our environment. For example, Israel does a great job in taking innovative ideas from entrepreneurs to incubation, many times inside of universities, and then spinning them into companies which later become part of the global value chain. In the process, this small country has created at least 150 NASDAQ listed high tech firms. Innovation to incubation to wealth creation – a formula that works very well there. We could certainly learn a lot from that model.”

Future of Indian semicon industry
So, how does Dr. Pradip Dutta see the Indian semicon industry, going forward? He said: “The Indian semiconductor industry is now poised at a very interesting juncture. While the MNCs are designing chips at the bleeding edge, we see a lot of high quality work being done by the design service companies and also local start-ups. Incidentally, the start-up scenario is quite active in the system space. This ties in with the ESDM focus of our industry. 

Round-up 2010: Best of semiconductors

Right then, folks! This is my last post for 2010, on my favorite topic – semiconductors. If 2009 was one of the worst, if not, the worst year ever for semiconductors, 2010 seems to be the best year for this industry, what with the analyst community forecasting that the global semicon industry will surpass the $300 billion mark for the first time in its history!

Well, here’s a look at the good, the bad and the ugly, if available for otherwise what has been an excellent year, which is in its last hours, for semiconductors. Presenting a list of posts on semiconductors that mattered in 2010.

Top semiconductor and EDA trends to watch out for in 2010!

Delivering 10X design improvements: Dr. Walden C. Rhines, Mentor Graphics @ VLSID 2010

Future research directions in EDA: Dr. Prith Banerjee @ VLSID 2010 — This was quite an entertaining presentation!

Global semicon industry on rapid recovery curve: Dr. Wally Rhines

Indian semicon industry: Time for paradigm shift! — When will that shift actually happen?

Qualcomm, AMD head top 25 fabless IC suppliers for 2009; Taiwan firms finish strong!

TSMC leads 2009 foundry rankings; GlobalFoundries top challenger!

ISA Vision Summit 2010: Saankhya Labs, Cosmic Circuits are Indian start-ups to watch at Technovation 2010!

ISA Vision Summit 2010: Karnataka Semicon Policy 2010 unveiled; great opportunity for India to show we mean business! — So far, the Karnataka semicon policy has flattered to deceive! I’m not surprised, though!

Dongbu HiTek comes India calling! Raises hopes for foundry services!!

Indian electronics and semiconductor industries: Time to answer tough questions and find solutions — Reminds me of the popular song from U2 titled — “I still haven’t found what I’m looking for”!

What should the Indian semicon/electronics industry do now? — Seriously, easy to say, difficult to manage (ESDM)! 😉 

Mentor’s Wally Rhines on global EDA industry challenges – II

Dr. Wally Rhines, chairman and CEO, Mentor Graphics.

This is the concluding part of my discussion with Dr. Walden (Wally) C. Rhines, chairman and CEO, Mentor Graphics.

EDA’s role in modeling and photomask correction
I asked Dr. Rhines about the future of EDA’s role in modeling and photomask correction. He said that in just a decade, resolution enhancement has grown from zero to over $200 million in annual revenue for the EDA industry.

“Almost all of this revenue is concentrated in two EDA companies. The value of this EDA software is clearly recognized by manufacturers. Mentor has many partnerships with manufacturers and a joint development program targeting 20nm resolution enhancement with IBM.”

Handling 22nm and sub-22nm levels
Next, with new process technology nodes becoming quite the talk of the desgin community, what does EDA now need to do at 22nm and sub 22nm levels.

Dr. Rhines said: “We have been working with our customers on this for quite some time now and are in fact well down this path. We think that most of the problems have been solved, or are solvable. Obviously, most of the issues here revolve around the lithography and manufacturability, but the EDA industry has been leading this since optical proximity correction became a key technology for the fabs quite some time ago.”

Density area savings
In an earlier discussion, the issue of how compelling would integration density area savings remain by going to new nodes had come up. I have to repeat this question, as it still seems to remain an issue.

So, how long will the integration density area savings you get by going to new nodes remain compelling?

“Hard to say!” noted Dr. Rhines. “We can see a path to 15nm with the traditional 193nm immersion lithography, and we usually surprise ourselves in our ability to go farther than we think we can. However, even if density slows down, this is but one way to achieve the continuous performance improvements that we’ve seen over the years in silicon.

“3D silicon, for instance, holds the promise of allowing us to continue to grow performance without necessarily doing it by just continuing the process shrink. Logic and memory have been on a predictable “learning curve” since the vacuum tube and I don’t expect that learning curve to deviate anytime in the foreseeable future.”

Mentor's Wally Rhines on global EDA industry challenges – I

Dr. Wally Rhines, CEO and chairman, Mentor Graphics.

It has always been such a pleasure meeting Dr.  Walden (Wally) C. Rhines, CEO and chairman, Mentor Graphics Corp. During his recent visit to India, I managed to enter into a discussion with him regarding various issues facing the global EDA industry.

Part one of the discussion looks at the industry, as well as EDA related issues such as predictability, verification and IP integration, how can Mentor help start-ups address EDA challenges, and going about software-to-silicon verification. May I also take this opportunity to thank my good friend, Mentor’s Veeresh Shetty.

I began by asking Dr. Wally Rhines about the fortunes of the global EDA industry and what’s it going to be like in 2011?

He said: “The EDA industry typically follows the recovery in semiconductor industry R&D spending by six to 12 months. Mentor’s strong results in Q3 (with 60 percent growth in bookings) suggest that the recovery has already started. In our third quarter conference call, we indicated to our investors that 2011 looks like a good year as well.” 

Local know-how, innovation (Jugaad) keys to realizing semicon/electronics growth in India

“We can’t just rely on making chips,” said Neeraj Paliwal, VP and NXP India country manager, while delivering his keynote: Semiconductor products for Indian market – leapfrog R&D workforce to product creation, at the recently held Mentor Graphics U2U conference. Local know-how and innovation hold the keys to realizing growth in the Indian context.

According to him, the semicon industry has evolved from initially being technology driven to customer driven, and lately, society driven. Paliwal listed four key macro growth drivers in electronics: energy efficiency, connected mobile devices, security and health.

Energy efficiency
* Efficient power conversion and low stand-by power.
* Energy-saving lighting and back-lighting.
* Energy conservation through demand side management.
* Electric/lighter vehicles, intelligent traffic management.

Connected mobile devices
* Proliferation of mobile data usage, wireless infra build-out.
* Smart mobile devices: always-on, multimedia, location-based.
* Connected car, many broadcast & connectivity standards.
* New user interfaces (e.g., touch, joystick).

Security
* Secure mobile transactions and secure identity.
* Authentication, tagging and tracking.
* Car and home access, security and remote diagnostics.
* Radar and (body) scanning installations.

Health
* Personal healthcare and portable emergency devices.
* Connected hearing aids and implantable devices.
* Car safety and comfort.
* Electronic diagnostics.

Jugaad — Indian flavor of innovation
In the Indian context, local know-how holds the key to realizing growth! Here, Paliwal introduced “Jugaad” an Indian word, which simply means an improvisational style of doing things or innovation, largely driven by or making use of scare resources available.

There is a need to develop an innovation mindset with the focus on revenue growth to reach new markets. Well, it should help when the innovations look at solving local problems first, and later, go on to address related or similar international problems.

Some examples of Indian innovations, include Tata’s water filter for rural poor for $20, which does not run on electricity; and Tata’s Nano car, which aims to reach the bottom of the pyramid. Also, John Deere’s weather recession with help from innovation. In fact, innovation could well be India’s next global export.

India already has a National Innovation Council, with the aim to provide a broader plaform for innovation to redefine the understanding of innovation and move beyond the formal R&D paradigm. Another example of innovation — wireless kiosks for rural India.

EDA and emerging system design challenges: Dr. Wally Rhines

Dr. Wally Rhines.

According to Dr. Walden C. Rhines, CEO and chairman, Mentor Graphics, the emerging system design challenges likely to shape the industry in the coming decade are:

* Design for low power.
* Optimizing for performance and power.
* Functional verification complexity explosion.
* Place and route timing and power closure.
* Physical verification complexity.
* Manufacturing yields.
* Increasing cost of design.
* Macro system integration.

He was delivering the keynote titled EDA and emerging system design challenges at Mentor Graphics’ U2U India conference in Bangalore.

First, Dr. Rhines highlighted that the EDA market churn is often confused with industry consolidation. EDA requires specialization. The #1 supplier in each EDA product segment averages 66 percent+ market share. However, the traditional EDA market has not been growing.

EDA market snapshot
The synthesis market trend has seen a 2.7 percent CAGR, with a 10-year average of $293 million. The market size was $273 million in 2008, and slid to $243 million in 2009. In 2010, after the first two quarters, it is approximately $125-$130 million.

The RTL simulation market trend has seen a -0.3 percent CAGR, with a 10-year average of $365 million. The market size was $394 million in 2008, and slid to $345 million in 2009. In 2010, after the first two quarters, it is approximately $150 million.

The IC layout verification market trend has seen a 0 percent CAGR, with a 10-year average of $199 million. The market size was $199 million in 2008, and slid to $187 million in 2009. In 2010, after the first two quarters, it is approximately $80-$90 million.

The IC physical implementation market trend has seen a 2.4 percent CAGR, with a 10-year average of $559 million. The market size was $549 million in 2008, and slid to $448 million in 2009. In 2010, after the first two quarters, it is approximately $210 million.

The total PCB/MCM design market trend has had a 10-year average of $484 million. The market size was $535 million in 2008, and slid to $490 million in 2009. In 2010, after the first two quarters, it is approximately $220 million. PCB design has seen growth from analysis, design for manufacturing and new emerging markets.

Women power, RVCE rule at first annual Karnataka VLSI and embedded systems awards

RVCE, E&C, the winners!

It is always a pleasure to witness women power in technology! More especially, in India!! To my pleasant surprise, and am sure, of many others present, women power was aplenty at the first annual Karnataka VLSI and Embedded Systems Awards distribution ceremony held today at the RV-VLSI Design Center, Bangalore.

First, the winners! Congratulations to each one of them on their achievement!

VLSI category
Winner: Suraj H, Vinay R, Vinaya Ajjampura and Vasudev Pai M, RVCE, E&C.
Title: Design and verification of 16-bit pipelined microcontroller.

Runner-up: Deepika, Deepthi MN, Divya V Nayak, RVCE, Telecom — an all-women team!
Title: Design and verification of stand-alone DMA controller.

Embedded category
Winner: Praseed Chandriki, Prashant Bhat, Anup Reddy, Manoranjan S, RVCE, E&C.
Title: Implementtion of media transport in VoIP and performance analysis through measurement of QoS.

Runner-up: Ashwini HV, Sayak Bhowmick, Shruthi BR, Shruti S. Rao, Global Academy of Technology, E&C.
Title: DARAM driver for VoIP router.

It was announced that Mentor Graphics, along with STMicroelectronics, will be sponsoring next year’s awards.

Dignitaries at the first annual Karnataka VLSI and embedded systems awards.

This year’s contest was initiated by RV-VLSI in close association with VTU, and sponsored by Mentor Graphics. Dr. Walden C. Rhines, CEO and chairman, Mentor Graphics, graced the occassion. Dr. V.S. Acharya, the Honorable minister for Higher Education, Planning and Statistics, Government of Karnataka, who could not make it to the event owing to pressing official work, had his message read out.

Other digitaries present on the occasion included Hanns Windele, VP Mentor Graphics (Europe & India), Ian Burgess, Higher Education Program, Mentor Graphics, CV Hayagriv, Trustee, Rashtreeya Sikshana Samiti Trust, and chairman, governing council, RV-VLSI Design Center, AVS Murthy, honarary secretary, Rashtreeya Sikshana Samiti Trust, and Dr. MK Panduranga Setty, president, Rashtreeya Sikshana Samiti Trust (RSST).

RV-VLSI can tape-out multi-billion transistor chip today!
Venkatesh Prasad, CEO, RV-VLSI Design Center, said it was his interaction with a visionary like Dr. MK Panduranga Setty, and the support of the board of trustees of RSST that made it easy for him to transition out of the industry and start RV-VLSI. The vision of RV-VLSI is to create a steady stream of well trained professionals with a low TTP (time to be productive). To achieve a low TTP, it had to do things different from a traditional academic institution.

That differentiation started with the name, RV-VLSI Design Center itself, rather than RVDI. Next, the institute procured a Sun data center to meets its complex needs. Next, it gained access to foundry technology from Tower Semiconductor and EDA software from Mentor Graphics. Prasad added, ‘RV-VLSI has the infrastructure to design and tape-out a multi-billion transistor chip today.”

Is enough being done for Indian industry-academia collaboration in VLSI education?

Do you, as a semiconductor/VLSI/EDA company, run university or educational programs for colleges and institutes? Am sure, you do!

Well, are you providing these various colleges and institutes with the latest tools and EDA software? Perhaps, yes! So, do you regularly check whether your tool is being used properly, or at all? What do you do if the tool remains unopened or unused? Okay, before all of that, are you even guiding the faculty and students to tackle real world problems associated with chip design?

Do the students (and the faculty) know the intricacies of 22nm, 32nm, 45nm, and so on? Are you able to assist students in taping out? Right, is the syllabus taught in all of these colleges good enough to produce the kind of talent and skills that the semiconductor/VLSI industry requires currently, and in the future? Is everything being taught, the latest?

As they say — it takes two to tango… and, it takes two hands to clap! To the Indian academia — how many among you are “really” serious about being trained on a regular basis by the semicon/VLSI/EDA industry? What have you all done about it so far, all of these years? How many colleges and institutes among you (and do you) regularly put up or raise your hand to the industry and say — we lack the knowledge in a particular area and need training – please help us!

The question is: what are you, as a semicon/VLSI/EDA company, doing about training the various faculty and the students in various colleges and institutions across India? Do you have a proper program in place for this activity? Well, is enough being done regarding the industry-academia collaboration in VLSI education in India? What more needs to be done?

Are you, as a college or institute teaching VLSI, happy with the quality of talent coming out? Are you really satisfied with the quality of B.Tech/M.Tech projects? Do you seek industry’s help regarding training on a regular basis? What steps do you take to reach out to them? And, what are you doing about it all? Do you take that initiative seriously?

For that matter, are there easy-to-use systems that enable effective and industry-relevant education? Are those being made use of properly? Can entry barriers be lowered for students and faculty so they can explore an IP idea that has business potential? How many of the colleges have done this? I know of some folks trying to develop such solutions, but that’s a separate story for another day!

Coming back on track, apparently, some semicon companies and few well known Indian institutes are really exceeding themselves, but the same story does not hold true everywhere. Why is it so?

There could be a variety of reasons, and not all are listed here. Is it a lack of initiative on part of the industry and the institutes? Don’t they even talk to each other? Are institutes not able to approach semicon companies and vice versa? Or, is it the locations of the institutes themselves? Is it that not all institutes are concerned about teaching their students how to solve real world chip design problems?

An industry friend had once remarked: As of the last three-four years, students from the Eastern part of India have no clear pathway that they can pursue to get into VLSI design. The reasons are — there are no training institutes in the East, which can teach Synopsys or Cadence tools or even the basics of Xilinx FPGA design.

A very interesting panel discussion titled Forging win-win industry-academia collaboration in VLSI education was held during the Cadence CDNLive India University conference.

Moderated by Dr. C.P. Ravikumar, technical director, University Relations, TI India, the panelists were Dr Ajit Kumar Panda from NIST Behrampur, K Krishna Moorthy, MD, National Semiconductor India, Dr K. Radhakrishna Rao, head, analog training, TI. India and R. Parthasarathy, MD, CADD Centre.

I have already covered Dr. Ravikumar’s remarks separately.

Let’s see what the other panelists have to say about all of this, and whether they have answers to all of the questions or problems. Well, this is another long post, so please bear with me! 😉

Cadence VLSI certification program (CVCP) aims to deliver 'industry grade' graduates

Cadence Design Systems presented a curtain raiser on the Cadence VLSI Certification Program (CVCP) during the CDNLive India University conference. The availability of trained manpower holds the key to sustained growth. Also, the first thing required to build a good product is to have a good design. Hence, the need for good chip designers.

Cadence already has over 300 program participant institutes in India. The company regularly conducts ‘train the trainer’  programs as well. This program has so far witnessed the tapeouts of five chips and includes IPs from 14 colleges.

Cadence has also started additional strategic programs. First, finishing schools — initiatives with some universities and Indian semiconductor houses. These have been established to bridge the skill gap. Cadence has seen some success in Hyderabad and Bangalore. It has also contributed to the industry demand of manpower. Cadence also has the Orcad training program.

Joint development activity has been happening within the industry-academia to provide a consistent quality of curriculum and develop broader penetration.

The enablers/catalysts are industry veterans, who accept their social responsibility of training upcoming engineers. Some of the first movers aer already Cadence’s training partners.

CVCP initiative
Cadence’s CVCP has been launched with objective of delivering graduates that are ‘industry grade’. It will also provide an incremental training approach, leading up from VLSI fundamentals to industry relevant skills.

The industry relevant leading edge course work has been developed and proven through various programs such as the Cadence-Brazil initiative. Graduates will undergo hands-on guided development projects. The CVCP’s duration is of 214 hours spread over six months. It offers the following:
* MTEch in VLSI.
* MTech in digital electronics.
* MTech in embedded systems.
* BE/BTech in ECE, EE, TC.

The course will be running concurrent to the ongoing degree. Cadence owns the course, which is delivered by CCTP with support from CDNS. NIST, Berhampur, in Orissa, is the first participant in the CVCP with a batch of 60 students.