R&D innovation: nano-scale to tera-scale

Justin Rattner, VP and Senior Fellow CTO, Intel Corp., while speaking at the recently held CXO Forum organized by the India Semiconductor Association (ISA), highlighted the various innovations Intel has created over the years and continues to do so.

There are some hurdles to innovation. For instance, success brings conservatism and then, there is the curse of high-volume manufacturing. It led to Andy Grove’s famous statement: “Only the paranoid survive”. Obviously, massive inertia and innovation do not blend. Rattner mentioned certain external hurdles, especially, anti-Innovation policies and standards that hamper innovation.

Moore’s Law drives innovation
Moore’s Law has been driving innovation at Intel. These have been in the form of high-K metal gate transistors at 45nm — the first new transistor architecture in 35 years! There’s more, in form of phase change memory (PCM) below 45nm, non-planar tri-gate transistor beyond 32nm, and carbon nanotube transistor

Some recent multi-disciplinary innovations include 45nm Core 2 Duo, Nehalem uArch, power management, quad core through package technology, Silverthorne/LPIA, USB/PCI Express, vPro, and WiMAX and 802.11n, respectively. Intel has made sustained Advances in silicon technology. In 2007, it developed 32nm SRAM with 1.9 billion transistors, with 32nm slated for 2009.

Sustained advances in micro-architecture include Intel Core — new microarchitecture 65nm (2006), Penryn compaction/derivative at 45nm (2007), Nehalem — new microarchitecture 45nm (2008), Westmere compaction/derivative 32nm (2009), and Sandy Bridge new microarchitecture 32nm (2010). “This shows our sustained microprocessor leadership,” added Rattner.

There are plans to further reinvigorate Intel architecture — by high throughput computing, IA programmability, ease of scaling for software, array of enhanced IA cores, and increasing teraflops of performance. Its 45nm Silverthorne is based on the Menlow platform and promises ‘Full Internet in Your Pocket.’

Intel has also made advances in integration and packaging, such as multi chip packages, Wifi + WiMAX, processor + chipsets + accelerators, 60 percent smaller CPU packages, and 100 percent lead-free technology*. By 2008, Intel is committed to having all 45nm CPUs halogen free.

Innovations in memory, communications
Intel has also made innovations in memory technology. Robson Technology, which has NAND Flash cache, has 1.5X faster application load times, has 1.5X resume from hibernate, gives 0.4W average power savings, and is used in the Santa Rosa platform.

The other innovation is solid-state drives. These are embedded in a range of devices, from handhelds to servers. Compared to HDDs, these give 1/10th the power, >10X performance, and are 1,000X more durable.

Innovations in communication technology include things like adaptive antenna and front-ends, digital CMOS radio, and reconfigurable baseband. Intel has also developed the world’s 1st TeraFLOPS supercomputer on a die. It features 80 cores, 1TFLOP at 62W, and 256 GB/s bisection.

Intel has also unleashed the era of tera. These are in the form of tera bits –- Si Photonics and tera bytes –- 3D stacked memory. The latter includes 256KB SRAM per core, 4X C4 bump density, and 3200 thru-silicon vias.

Similarly, Intel’s innovation in tera-scale software include RMS workloads, C++ for parallelism, Ct for nested data parallelism (race-free irregular parallel computation), and hardware assisted STM C transactional memory, which ensures concurrent access with no errors.

Intel has also done innovations for emerging regions. Rattner touched upon Research (at the Berkeley Lablet), which involves a long-distance WiFi solution: 6Mb/s at 100+ km. This has been tested at the Aravind Eye Hospital in Tamil Nadu. It has allowed doctor/patient videoconferences. Thirteen rural villages have been connected so far, going on to 50 villages. The impact has been tremendous — 2,500 exams per month, over 30,000 so far; cataracts, glaucoma, cornea problems have been diagnosed; and 3,000 people have had their vision restored so far.

Intel has also been a champion in innovating through collaboration. These have been in form of academic open-collaborative (pre-competitive research) — Carnegie Mellon, Berkeley, University of Washington; industrial partnerships (product differentiation) — an example being the ciscointelalliance.com, and consortium (ecosystem benefit) — via the ISA, Continua, Innovation Value Institute, Trusted Computing Group, etc.

Intel’s focus areas for 2008 include:
a) tera-scale computing — unleashing the next generation of applications.
b) Platform* on a chip (POC) — ‘Platform’ integration on chip with IA.
c) Trusted services — technologies for secure service opportunities.
d) Carry small, live large — context aware usage models and platforms.
e) Ultimate connectivity — connected ‘all-ways’ for future platforms.

Challenges for IC industry and Dr. Gargini's lessons

Those who were fortunate enough to attend the recently held SEMICON WEST in San Francisco had the pleasure of attending a great session on the past. present and future challenges for the IC industry by Dr. Paolo Gargini, Director of Technology Strategy at Intel.

For those who may not have the time to read this article, here’s a snippet of what Dr. Gargini had to offer. The first lesson, he said, was that, “Something right may still happen even when everything seems to be going wrong.” However, challenges that were continuously posed also needed to be addressed at the earliest, in order to keep moving forward.

Many also predicted several times that some limit would be reached – that chip development would never get below ten nanometers, or below five nanometers. However, the industry was able to produce components with a gate oxide at about 1.2 nanometers.

Later, the game changed to scaling, which led to Gargini’s second lesson – “Predictors of engineering limits have always been proven wrong by the right improvements.” Shrinking silicon technology of the 1990s kept the industry moving forward.

His third lesson was, “It would be wrong to believe that the right fundamental limits don’t exist.” The fourth lesson was, “It is wise to look for the right solutions before things start going wrong.” Dr. Gargini recalled how Intel had announced that 45nm generation was ready. That it included high-k metal gates was only disclosed this January giving Intel the time to work on yields, enhancements, reliability problems, etc.

Gargini quoted Gordon Moore as saying that introduction of high-k metal gates was the single most important innovation in semiconductor manufacturing of the last 40 years!

Interestingly, a few weeks ago, the PULLNANO Consortium announced breakthrough results for 32nm/22nm. Among other things, the PULLNANO consortium has fabricated a functional SRAM using innovative MOS transistors whose device architecture differs significantly from that of transistors used in 45nm technology node.

These transistors are built using a low power consumption approach based on Fully Depleted Silicon On Insulator (FDSOI), coupled with a gate stack composed of a high-K gate dielectric and a single metal electrode stack. This is said to be the first time that such a compact SRAM cell has been fabricated using FDSOI, high-k dielectric and metal gate together.

Coming back to Dr. Gargini, his fifth lesson was, “It would be wrong to delay taking action and not do the right thing at the right time.” According to him, there was a need for re-examining the opportunities for reviewing “old” theories and techniques that didn’t work on silicon.