INSIDE Contactless unveils SecuRead NFC solution for mobile handset market

INSIDE Contactless' SecuRead NFC solution for mobile handsets.

INSIDE Contactless has unveiled SecuRead, a breakthrough NFC solution for the mobile handset market. This chip will be integrated into production handsets by mid-2011.

SecuRead is a complete, system-in-package (SIP) NFC solution that makes it simple for mobile device manufacturers and NFC infrastructure providers to integrate all of the contactless, security and application functions required for a broad range of contactless NFC payment, transit, ID and access control applications.

According to the company, SecuRead features INSIDE’s award-winning MicroRead NFC controller, a high-performance, highly secure SLE 97-family secure element from Infineon, a GlobalPlatform-compliant Java Card OS from Giesecke & Devrient and INSIDE’s Open NFC protocol stack to provide a best-of-breed solution that helps mobile device manufacturers bring rich NFC capabilities to market more quickly.

Loic Hamon, VP of products and marketing for NFC at INSIDE Contactless, said that 2011 will be the inflection point for NFC with over 50Mu devices. There are multiple committed handset ecosystems. Also, there are wireless carrier commitments, consortia, initiatives, etc. Android is now a major market driver – outselling the iPhone.

As for the regional situation, the US is witnessing mobile payment (embedded secure element). Korea is seeing a replacement of T-money (transport, payment, loyalty), UICC based. In Nice, France, there will be multi-carrier, multi-service, UICC-based, national rollout in 2011.

Ecosystem alignments are needed, and business models have to be proven. Also, NFC peripherals will contribute to market acceleration.

View 3D TV, without glasses, today!

Did you ever want to watch the latest movie or ball game with flawless, immersive 3D images on your 2D LCD screen without using 3D glasses? I sure do! All the time!!

I even suggested to a semicon company recently, which is providing HD media processor SoCs, to highlight a solution, which will allow the man in the street to pick up the DVD of Harry Potter and the Deathly Hallows – Part 1, insert it into the player, and enjoy the movie on his TV in 3D! All of it, without wearing 3D glasses!

Sounds quite far fetched, isn’t it?

3D TV viewing possible on 2D TV, today!

See the future of 3D TV, with the naked eye, today, says 3DFusion!

Well, I believe, Stephen Blumenthal, president of 3DFusion, surprised everyone at the Paul Kagan 3D Market Media Conference at Waldorf Astoria Hotel on October 27 last month, when he, along with his partner Ilya Sorokin, invited the audience to visit the 3DFusion business suite, located upstairs in the Waldorf, to experience the picture perfect 3DFMax glasses free 3D ASD, and see a real time, live 3D stereo camera capture display!

Steve was  kind enough to share his landmark speech with me, as well. First up, many congrats to Steve and 3DFusion!

His opening line itsef is very interesting: “This is a historic day for me, as I started out as a TV repair man from Ithaca NY, and now today, we are introducing for the first time, a 3DTV, glasses free Broadcast Quality, Perfect Picture television platform, one destined I believe to replace 2D TV.”

“We are here to introduce a 3D technological advancement, which marries the classical 3D left/ right stereo pair, with a Math augmented, Depth Meta Data (DMD) approach. The addition of DMD to the stereo pair, results in an interactivityy giving the operator mastery over the 3D image. For the first time we can demonstrate an on the fly, real time, intervention with the 3D video signal path.

“What we have is a methodology of video signal integration with PC driven algorithms that support an ability to control signal parameters, which determine depth visuals on a variety of Auto Stereoscopic Displays. The 3DFMax DMD Algorithm approach mines the stereo depth information and converts it to META data which is inserted as the right field of the frame, replacing the right view, as a gray scale mapping.

“This data is auto converted by our Firmware, on the fly into 9 Multiviews as the key to the pixel per pixel orientation for the lenticular lens or lenticule, thereby controlling the depth cues. One 3DFmax video frame is composed of the left field as a full resolution view, with the Right field operating as a lightweight DMD map which may be re-rendered in real time, visible on the 3DFMax ASD screen, thereby providing instant correction and adjustment to the images depth visual cues.

Brocade launches VDX switches for virtualized, cloud-optimized data centers

Brocade recently launched what it claims is the industry’s first true Ethernet fabric switching solutions that are purpose-built for highly virtualized and cloud-optimized data centers.

Its VDX product family of Ethernet fabric switches makes use of Virtual Cluster Switching (VCS) technology. These are based on a scaled virtualized environment without adding network complexity, and enables building flexible, open and hypervisor-agnostic networks.

Brocade also launched the VDX 6720 switches – the first in VDX family. These feature 10 GbE wire-speed, low latency, LAN/SAN  convergence. They run on sixth generation fabric ASIC and proven O/S technology. The key things — you pay as you grow ports-on demand and low power usage.

What’s new?

Rajesh Kaul, country manager, Brocade.

So, what’s new about this switch? Rajesh Kaul, country manager, Brocade, said: “The technology underlying the Ethernet fabric — it has all of the resiliences of the fiber fabric and the simplicity of the Ethernet built on to it.

“Every point of the network is connected to every other point on the network — rather than the classical Ethernet. Also, we don’t use spamming tree protocol (STP). We use the TRILL protocol. In this case, every path is active.”

Brocade is working with the Internet Engineering Task Force (IETF) on a standard called Transparent Interconnection of Lots of Links (TRILL). This provides multiple paths via load splitting.

TRILL will allow reclaiming network bandwidth and improve the utilization by establishing the shortest path through Layer 2 networks and spreading traffic more evenly. Hence, the network can respond faster to failures.

Kaul added that these devices act on a layer 2 level. “Every device is intelligent and a master device. So, this is a masterless switch.”

Is enough being done for Indian industry-academia collaboration in VLSI education?

Do you, as a semiconductor/VLSI/EDA company, run university or educational programs for colleges and institutes? Am sure, you do!

Well, are you providing these various colleges and institutes with the latest tools and EDA software? Perhaps, yes! So, do you regularly check whether your tool is being used properly, or at all? What do you do if the tool remains unopened or unused? Okay, before all of that, are you even guiding the faculty and students to tackle real world problems associated with chip design?

Do the students (and the faculty) know the intricacies of 22nm, 32nm, 45nm, and so on? Are you able to assist students in taping out? Right, is the syllabus taught in all of these colleges good enough to produce the kind of talent and skills that the semiconductor/VLSI industry requires currently, and in the future? Is everything being taught, the latest?

As they say — it takes two to tango… and, it takes two hands to clap! To the Indian academia — how many among you are “really” serious about being trained on a regular basis by the semicon/VLSI/EDA industry? What have you all done about it so far, all of these years? How many colleges and institutes among you (and do you) regularly put up or raise your hand to the industry and say — we lack the knowledge in a particular area and need training – please help us!

The question is: what are you, as a semicon/VLSI/EDA company, doing about training the various faculty and the students in various colleges and institutions across India? Do you have a proper program in place for this activity? Well, is enough being done regarding the industry-academia collaboration in VLSI education in India? What more needs to be done?

Are you, as a college or institute teaching VLSI, happy with the quality of talent coming out? Are you really satisfied with the quality of B.Tech/M.Tech projects? Do you seek industry’s help regarding training on a regular basis? What steps do you take to reach out to them? And, what are you doing about it all? Do you take that initiative seriously?

For that matter, are there easy-to-use systems that enable effective and industry-relevant education? Are those being made use of properly? Can entry barriers be lowered for students and faculty so they can explore an IP idea that has business potential? How many of the colleges have done this? I know of some folks trying to develop such solutions, but that’s a separate story for another day!

Coming back on track, apparently, some semicon companies and few well known Indian institutes are really exceeding themselves, but the same story does not hold true everywhere. Why is it so?

There could be a variety of reasons, and not all are listed here. Is it a lack of initiative on part of the industry and the institutes? Don’t they even talk to each other? Are institutes not able to approach semicon companies and vice versa? Or, is it the locations of the institutes themselves? Is it that not all institutes are concerned about teaching their students how to solve real world chip design problems?

An industry friend had once remarked: As of the last three-four years, students from the Eastern part of India have no clear pathway that they can pursue to get into VLSI design. The reasons are — there are no training institutes in the East, which can teach Synopsys or Cadence tools or even the basics of Xilinx FPGA design.

A very interesting panel discussion titled Forging win-win industry-academia collaboration in VLSI education was held during the Cadence CDNLive India University conference.

Moderated by Dr. C.P. Ravikumar, technical director, University Relations, TI India, the panelists were Dr Ajit Kumar Panda from NIST Behrampur, K Krishna Moorthy, MD, National Semiconductor India, Dr K. Radhakrishna Rao, head, analog training, TI. India and R. Parthasarathy, MD, CADD Centre.

I have already covered Dr. Ravikumar’s remarks separately.

Let’s see what the other panelists have to say about all of this, and whether they have answers to all of the questions or problems. Well, this is another long post, so please bear with me! 😉

Cadence VLSI certification program (CVCP) aims to deliver 'industry grade' graduates

Cadence Design Systems presented a curtain raiser on the Cadence VLSI Certification Program (CVCP) during the CDNLive India University conference. The availability of trained manpower holds the key to sustained growth. Also, the first thing required to build a good product is to have a good design. Hence, the need for good chip designers.

Cadence already has over 300 program participant institutes in India. The company regularly conducts ‘train the trainer’  programs as well. This program has so far witnessed the tapeouts of five chips and includes IPs from 14 colleges.

Cadence has also started additional strategic programs. First, finishing schools — initiatives with some universities and Indian semiconductor houses. These have been established to bridge the skill gap. Cadence has seen some success in Hyderabad and Bangalore. It has also contributed to the industry demand of manpower. Cadence also has the Orcad training program.

Joint development activity has been happening within the industry-academia to provide a consistent quality of curriculum and develop broader penetration.

The enablers/catalysts are industry veterans, who accept their social responsibility of training upcoming engineers. Some of the first movers aer already Cadence’s training partners.

CVCP initiative
Cadence’s CVCP has been launched with objective of delivering graduates that are ‘industry grade’. It will also provide an incremental training approach, leading up from VLSI fundamentals to industry relevant skills.

The industry relevant leading edge course work has been developed and proven through various programs such as the Cadence-Brazil initiative. Graduates will undergo hands-on guided development projects. The CVCP’s duration is of 214 hours spread over six months. It offers the following:
* MTEch in VLSI.
* MTech in digital electronics.
* MTech in embedded systems.
* BE/BTech in ECE, EE, TC.

The course will be running concurrent to the ongoing degree. Cadence owns the course, which is delivered by CCTP with support from CDNS. NIST, Berhampur, in Orissa, is the first participant in the CVCP with a batch of 60 students.

Forging win-win industry-academia collaboration in VLSI education

Despite all the talk of semicon/VLSI going around in India, is the correct curriculum really being taught in the various institutes? Is the academia able to prepare students to be better equipped to tackle today’s world’s problems? Does the student have sufficient skills that the Indian (and global) semicon industry recruiters are looking for? Is the student, and the academia semiconductor-industry ready sufficiently?

Panel discussion on industry-academia collaboration in VLSI education.

There was a lively panel discussion titled: Forging win-win industry-academia collaboration in VLSI education during the post lunch session of CDNLive India University conference.

I remember last year’s CDNLive India panel discussion quite clearly! There was an entertaining session on how to prepare the students to be semiconductor industry read. It remains a top read till date!

This year’s panel discussion was moderated by Dr. C.P. Ravikumar, technical director, University Relations, Texas Instruments India.

The panelists were:
* Prof Ajit Kumar Panda, NIST Behrampur, Orissa.
* K Krishna Moorthy, MD, National Semiconductor India
* Dr K. Radhakrishna Rao, head, analog training, TI.
* R. Parthasarathy, managing director, CADD Centre.

Starting the discussion, Dr. Ravikumar said that the semicon industry is currently seeing fast paced growth. New knowledge is getting added every year. The semicon industry has been present in India for over 25 years now, and counting.

There is a varied expectations from the academia in India. For instance, should they teach fundamentals or skills? Do they have silicon experience, or can the institute bring this about on its own? What is important — going up or down the abstraction level?

Or, should VLSI education be introduced at the graduate level or should it be in the Masters leel? There are several gaps in the curriculum itself. What can the industry do about those gaps?

Dr. Ravikumar said: “TI is celebrating 25 years. The kinds of problems TI is working on today are vastly different from the times when it had started in India. Today, it is doing large SoCs. The industry has hige expectations from the academia.

People, he added. seem to have diverse opinion on VLSI. Even at abstraction levels, we can talk about power, circuit design, larger blocks, etc. You will likely hear different sort of viewpoints depending on who you are talking to.

He said: “A lot of effort is being put into the formation of new M Tech programs in VLSI across various institutes. Wheher the students passing out from these institutes will find employment in the Indian semiconductor industry- is also a point of debate. Again, I’ve seen VLSI being talked about in the graduate level as well.”

Since there were four panelists, I shall add their views in a separate post. Stay tuned, folks! 😉

What does it take to be an entrepreneur!

Why exactly do (or did) you choose to become an entrepreneur? Do you have a brilliant product idea? Do you see a large unmet opportunity for your idea?

Rajesh Subramaniam, MD, Walden India Advisors.

Or, did you leave your job and become an entrepreneur as you either hated your boss or job? Did you think it is fashionable to be on your own? Did you think you could become a ‘trend setter’? Will a VC fund that great idea of yours? Is that idea going to be sustainable in the long run? Well, the reason could just about be anything!

Rajesh Subramaniam of Walden India Advisors Pvt Ltd presented an interesting talk on ‘What does it take to be an entrepreneur’ during the CDNLive India University conference — apparently aimed at the several students among the audience.

Ideation and execution
The first thing as an entrepreneur is to have clear ideation and execution. Ideation and a clear path to execution are the most important attributes to get you started. The idea should be conceived from a real gap that exists in the system, and not what you perceive it to be! Also, it is advised that you always stay with demand, not supply.

Subramanian  advised budding entrepreneurs to talk to as many people to see validity of your hypothesis. If you cannot sell your product, then nobody can. Also, if it is not scalable, it is not going to get out of your garage.

Also, you are not going to cut much ice in case you turn out to be a ‘me-too’ company. Always look for that differentiator! Finally, God is in execution — as they say: “In God we trust, the rest we check.”

Creating commercial IP in academic community

Dr. Rajat Gupta, MD, Beceem.

“The only community that can develop IP for the next generation is the academia and institutes,” said Dr Rajat Gupta, managing director, Beceem Communications Pvt Ltd, while presenting the guest keynote during the CDNLive India 2010 University Conference.

India is currently an attractive market. Its 50 million+ middle class can well become the preferred target for all product companies in the world.  In this context, what can the academic community do to stimulate product development in India? And, how can they engage in early technology development?

Further, can this large resource pool be mobilized to collaborate to create a massive IP ecosystem that is both commercial and free?

He said: “If there is wide ranging collaboration within the academia, the current duplication that’s happening can go away. This collaboration can also become a vehicle for a different type of industry-academia collaboration.

“Unless we are able to create  a basic ecosystem, we cannot get there. Unfortunately, leading edge work in VLSI does not happen that much in India at the moment. We need to make that happen.”

Understanding layers in IP creation
Gupta enlightened the audience about understanding the multiple layers involved in IP creation. For instance, in foundation IP, standard cell library and I/O library are at the core. Once you start building, people will realize that there are lots of interesting things to learn.

Pressing need to build capabilities in universities: Jaswinder Ahuja

CDNLive India held its University Conference today. Welcoming the delegates — largely made up of faculty members from various institutes across India and students, Jaswinder Ahuja, corporate VP and MD, Cadence Design Systems (I) Pvt Ltd, highlighted that there are over 300 universities in India that have access to Cadence’s EDA software.

Jaswinder Ahuja, corporate VP and MD, Cadence Design Systems (I) Pvt Ltd.

Dwelling on how Cadence went about developing its University program in India, he said that the EDA vendor first started its faculty training program. “As a next step, we wanted the students to develop some real designs, and to innovate. So, we launched the Cadence Design Contest. We have had this for five to six years now. This year, we split the contest into Masters and Bachelors levels.” Cadence started the  University conference last year.

Ahuja re-iterated, “It is important that we develop a community — where the faculty and students come together and share their experiences.” A visiting professor from Gerrmany shared his experiences in Europe during last year’s CDNLive India University conference.

Challenges in university ecosystem
Ahuja added: “This year, we have started the Cadence VLSI Certification Program (CVCP). The whole idea is to ensure is that through the curriculum, labs and the like, we can help the student to be industry ready from day one!

“Right now, it takes anywhere from six months to two years to achieve that — which s simply, productive time lost. Our goal is to build capabilities in the universities. We also have two pilots going on under CVCP. Once those are over, we will be ready to scale up.

“One of the challenges that we face when we look at the university ecosystem today — the faculty is the backbone of the academic infrastructure. It is important that the faculty is world class. If some of our best and briightest don’t make the choice to be part of faculty, then the entire industry is at threat. Those who have the passion to teach and impart education, should definitely stick around.”

He noted that the government of India is also very keen on investing in education. That’s going to improve prospects for higher education and for those who would want to get into the education field. It is said that some of the bills that have to be passed in the Indian Parliament are built around enhancing and growing higher education.

Semicon/EDA industry needs to figure out how to use the social media!

Cadence's Rahul Arya and John Bruggeman.

At the fag end of day 1 of CDNLive India 2010, I had the opportunity to interact with John Bruggeman, CMO, Cadence Design Systems and Rahul Arya, director, marketing and technology sales, Cadence Design Systems (I) Pvt Ltd.

A week ago, I’d written a post: Is social media really helping semicon/VLSI firms? Of course, there was a session organized by EDA Consortium (EDAC), titled: Does Social Media Reach the Engineers You Want or Waste Your Time?

Having earlier had a chat with Karen Bartleson, a panelist at the EDAC event, I thought it best to get  John’s views on some of the issues, since the EDAC panel had representation from Cadence (it wasn’t John) as well!

Lot more needs to be done on social sites
First, it is well known that the adoption of social media is at its infancy in the semicon.VLSI industry. In some other industries, the adoption is much faster. Why has it been this way, so far?

Bruggeman said: “We have an ageing population in our design community, more so than the other technology industries. So, we have been slower in adopting. The pickup on Twiter has been slow.

“We need to do whatever we can do to accelerate. We have heavily invested in bloggers and are also into driving social media. Cadence has two bloggers on staff. The blogs are promising. However, in some of the social media sites, a lot more needs to be done.” That’s quite an honest answer!

Are you building communities?
So, how are semicon/VLSI firms using the social media to build communities? Are you building or attempting to build communities? What is that particular community doing?

He added: “We need to figure out how, as an industry, should we use social media. How do you get a community of users to engage in an open dialog? We haven’t got anywhere near at developing a community. We also have to expand beyond blogging.”

Is the social media really helping reach out to design engineers? Are companies hiring via social media sites?

According to Bruggeman, every recruiter of note is now involved in LinkedIn. “Hirings are happening there. Design engineers are also going there to get hired, and not merely for free exchange of information. This is where engineers can talk to engineers,” he noted. “However, it will be interesting to see whether a commuity can be developed. So far, social media has managed to reach out to design engineers only a little bit.”