Overview of emerging power management opportunities

First, I must thank my friends, Lou Hutter, SVP and GM, Analog Foundry Business Unit, and Aabid Husain, VP of sales and marketing, from Dongbu HiTek Semiconductor, for sharing the presentations made during an EE Times virtual conference on emerging power management opportunities held on Sept. 16.

The conference participants were:
* Stephan Ohr, panel moderator and research director, Analog and Power Semiconductors, Gartner Inc.
* John Pigott, Freescale fellow, and analog IC guru and designer, Freescale Semiconductor.
* Ralf J. Muenster, director strategy and business development, National Semiconductor.
* Wayne Chen, VP for Technology and Operations, Triune Systems.
*  Lou N. Hutter, SVP and GM, Analog Foundry Business Unit, Dongbu HiTek Semiconductor.

Gartner’s Ohr started by indicating Gartner’s position on power management products. The standard analog ICs were a $15.2 billion market globally in 2009. Voltage regulators made up $7,394 billion, amplifiers $2,675 billion, data converters $2,567 billion, other analog $1,331 billion, and interface ICs $1,198 billion, respectively.

Voltage regulators – power management ICs accounted for 48.8 percent of the analog market. Voltage regulators continue to show strongest growth, growing at a CAGR of 11.1 percent for the period 2009-2014.

Power management ICs forecast
The global revenue forecast for power management ICs by market segment is as follows:

Military and aerospace: This is likely to grow at a CAGR of 3.2 percent during 2009-14.
Industrial/medical: This is likely to grow from $1,118 million in 2009 to $1,779 million in 2014, at a CAGR of 9.7 percent.
Automotive: This is likely to grow from $415 million in 2009 to $622 million in 2014, at a CAGR of 8.4 percent.
Communications: This is likely to grow from $529 million in 2009 to $988 million in 2014, at a CAGR of 13.3 percent.
Wireless: This is likely to grow from $1,353 million in 2009 to $2,149 million in 2014, at a CAGR of 9.7 percent.
Storage: This is likely to grow at a CAGR of 13.3 percent during 2009-14.
Computing: This is likely to grow from $2,114 million in 2009 to $4,013 million in 2014, at a CAGR of 13.7 percent.
Consumer: This is likely to grow from $1,627 million in 2009 to $2,564 million in 2014, at a CAGR of 9.5 percent.

Server and wired communications remain the biggest drivers.

Emergence of BCD technology
Lou Hutter from Dongbu HiTek discussed the technology considerations for emerging power management markets. He focused on the emergence of BCD (Bipolar/CMOS/DMOS) technology.

There are multiple benefits of BCD technology. These include integration of bipolar, CMOS, and DMOS components. It enables the integration of logic, analog control, and power on same die. It also enables high-and low-voltage, and high-and low-power functions on same die. BCD further enables reduced chip count, and improves reliability through fewer package interconnects. It also enables reduced BOM costs.

Emerging markets, such as automotive, solar and energy harvesting, stand to benefit from BCD. Dongbu is offering the 0.18um platform, which boasts of IP portability and more. Dongbu is offering the BD180LV-30V power process (Epi), to be followed by the BD180LV-30V power process (Non-Epi) in 3Q10, the BD180X 40-60V power process in 4Q10, and finally, the HP180 precision analog in 2Q11.

Hutter explained the BD180LV-30V Optimized Power and BD180X – 60V Optimized Power processes. Optional modules in Dongbu Hitek’s BCD technology include Schottky Diode, thick Cu, PLDMOS, NVM, low power CMOS, low noise CMOS, respectively.

Cadence's focus — systems, low power, enterprise verification, mixed signal and advanced nodes

I recently had the opportunity of meeting up with Nimish Modi, Senior Vice President, Research and Development, Front-End Group, Cadence Design Systems, along with Rahul Arya, Marketing Director, Cadence Design Systems (I) Pvt. Ltd.

Modi provided a perspective on how solutions from the EDA sector help the electronic design industry improve productivity, predictability and reliability of design processes, especially verification. Design verification is the process of ensuring that a chip design meets its specifications.

According to him, today’s product development ecosystem comprises of three driving forces — productivity, predictability and reliability. “We are clearly at the core of product development. We have a very strong breadth and depth. There is a layer of solutions we have integrated with our product offerings,” he added.

He highlighted that Cadence’s solutions consist of integrated point tools, as well as recommended use models. It also has a very strong services offering.

Focus on five key areas
Currently, Cadence is focusing on five key areas — systems, low power, enterprise verification, mixed signal and advanced nodes. “We have a solutions oriented approach across the board,” Modi said.

On systems, it is key to focus on gaining more productivity. Modi said: “This can be done by raising the level of abstraction. The technologies available to address ESL have been around for a while, each one addressing a piece of the puzzle. The need is there for seeing tremendous improvements in that. Here, Cadence’s C-to-Silicon Compiler comes in.”

“The other piece is — it has incremental synthesis capabilities. A third thing — it is connected to the downstream flow. This is the foundation of our systems strategy,” said Modi.

Coming to the systems design and verification strategy, the first component involves planning and management. “We have an enterprise manager,” he added. Cadence has been a leader in the hardware assisted verification with rich VIP/SpeedBridge portfolio. It has enabled a move to TLM driven design and verification flow. Cadence also delivers unique system power exploration, estimation and optimization flow. It provides unique hardware/software co-verification capabilities (Incisive Software eXtensions) as well.

Low power strategy
On Cadence’s low power strategy, Modi highlighted three components — implementation, verification and design. “The innovation was the ability to create a power format to capture the design intent. We are committed to providing flow operability as well. We want customers to make use of advanced power management techniques,” he added.

“We have the superior low power technology,” he claimed, referring to the Power Forward Initiative (PFI). “Look at technology — that is proven. The format is a means to the end. We are also working on providing more capabilities in the power exploration space. We are working under different aspects.

“You can do power analysis on the IP block; there’s C-to-Slicon, which has power as a function; multi-supply voltage will be a component of our synthesis solution. All of these vectors are driving the power exploration space. Seventy percent of chips’ power is determined at or before the RTL stage,” said Modi.

Cadence has a closed loop verification methodology. At each stage, you can go back and make sure you can be consistent with what’s there upfront.

Enterprise verification strategy
On enterprise verification, Cadence’s approach is plan-to-closure. Predictability — utilize executable plans and metrics that predict functional closure; productivity — effectively deploy methodolgy driven multispecialist flows. with VIP and multiproduct automation; and quality — reduce risk of functional bugs at tape-out at various project stages.

Modi added: “Our verification IP portfolio is also very critical. The depth of our portfolio is the broadest in the industry. In verfication, the actual TAM is growing. We are getting opportunities as well. Multi dimensions of enterprise verification are being taken care of by us.”

Interesting that all EDA companies have focused on verification! Why now and why not earlier? Modi said: “We’ve been in this area for a while. We have pioneered the new approaches. The goal is: how do you know it is good enough to hit the tapeout button? Our goal is to raise the confidence of customers.”

He added: “We are coming uo with a hybrid model. We are engaging with customers at this point of time. We came up with multi-language support in OVM. We have 30+ verification IP portfolios.”

Trends in complex SoCs
Today, it is largely a mixed signal world. Mixed signal IC revenue has been increasing faster than the rest of the industry. It is driven by applications, including wireless devices, consumer and DTV, and automotive.

Modi said: “There is a genuine need to support natively analog behavioral models in a digital centric verification environment. Mixed signal is a larger percentagre of area and effort.”

Coming down to advanced nodes, it is no surprise that Cadence definitely supports MCMM (multicorner and multimode). “It is part of our Encounter Digital Implementation System,” added Modi.