Synopsys' Galaxy Custom Designer tackles analog mixed signal (AMS) challenges

Synopsys Inc. recently unveiled its Galaxy Custom Designer solution, the industry’s first modern-era mixed-signal implementation solution. Architected for productivity, the Galaxy Custom Designer leverages Synopsys’ Galaxy Design Platform to provide a unified solution for custom and digital designs, thereby enhancing designer efficiency.

Galaxy Custom Designer delivers a familiar user interface while integrating a common use model for simulation, analysis, parasitic extraction and physical verification. It is the first-ever implementation solution built natively on the OpenAccess database for legacy designs as well as a new componentized infrastructure offering unprecedented openness and interoperability with process design kits (PDKs) from leading foundries.

Subhash Bal, Country Director, Synopsys (India) EDA Software Pvt. Ltd, highlighted three key features: One, it is architected for productivity. Two, it is a complete custom design solution. And three, it is based on an open environment.

The key question: why the Galaxy Custom Designer, and why now? Simple! The modern AMS era is characterized by interdependent custom and digital functions; analog IP is now mainstream; and there is the phenomena of an increased embedded memory. Current solutions are said to possess limited horizon. Hence, Galaxy!

A new solution is said to be the need of the hour, which is complete — verification and implementation, with common models, extraction, analysis. Re-spin is not an option. Next, unified implementation, which addresses both custom and cell based needs. Custom and cell based functions are highly interdependent. Also, close to 100 percent of designs today are AMS.

Finally, the solution has to be open and portable. This accelerates the design cycle and IP portability. Also, quicker access to process details is a must! Architected for productivity, Galaxy Custom Designer has a similar look and feel, and works using fewer clicks — three as against six!

Galaxy Custom Designer’s Schematic Editor has productivity enhancers such as real-time connectivity, on-canvas editing and smart connect. Similarly, productivity enhancers for its Layout Editor include push button DRC and Extract, standard TCL and Python PCells, and auto via and guard ring generation. The WaveView Analyzer has features such as highest capacity and performance, complex analysis toolbox, and an automated TCL verification scripting.

A unified platform for cell and custom means superior ease of use, performance, capacity and data integrity. Open and portable, it facilitates plug-and-Play IP as well as standards based PDK, which means one PDK for all tools, added Synopsys’ Bal.

The IPL (Interoperable PDK Libraries) is an industry alliance established on April 2007 to collaborate on the creation and promotion of interoperable process design kit (PDK) standards.

Wipro Technologies has been among the early users of the Galaxy Custom Designer. I also managed to speak with Anand Valavi, Group Head, Analog Mixed-Signal Group, Wipro Technologies.

Valavi said: “From an EDA tool perspective, in AMS area, the amount of productivity is a lot less than in the digital area. The per transistor productivity for a digital designer is several magnitudes higher than an analog designer.”

The methodology is definitely not as evolved as in the digital area. According to him, ‘This productivity will now increase for analog and AMS areas, and people can do a lot more complex designs in a shorter period of time. There has been a lot of integration.”

On the salient features or enhancements, he said there have been reasonably good improvement in several areas. One, there is an alternative, now, and that brings a lot of advantages. Two, when you take it down to next level, there are several other technical reasons.

Valavi added that an integrated environment definitely improved the productivity. There are other minor things. When you start using it, there are things that helps technical users — for example, an on-canvas editing. Also, the usage or collaborative results in the iPDK libraries will improve the effectiveness in chips designs that are churned out. “It will surely give people working in analog design area a choice,” he noted.

Mentor on EDA trends and solar/PV

This is a continuation of my recent discussion with Joseph Sawicki, vice president & GM, Design to Silicon Division, Mentor Graphics.

There have been whispers that the EDA industry has been presently lagging behind semiconductors and is in the catch-up mode. “That’s a matter of perspective. There are definitely unsolved challenges at 32nm and 22nm, but the reality is that we are still in the technology development stage,” he says.

For EDA tools that address implementation and manufacturing issues (i.e., Mentor design-to-silicon products), there are dependencies that cannot be fully resolved until the process technology has stabilized. Mentor Graphics is laying the groundwork for those challenges and working in concert with the process technology leaders to ensure that our products address all issues and are production-worthy before the process technology goes mainstream.

On the other hand, although Mentor’s products are fully-qualified for 45nm, there have only been a handful of tapeouts at that node, so for the majority of customers, we are ahead of the curve.

On ESL and DFM as growth drivers
ESL and DFM are said to be the new growth drivers. Sawicki adds: “As Wally Rhines has said in his public presentations, system level design and IC implementation are the stages of development where there are the most challenges, and therefore the most opportunities. To continue the traditional grow spiral that the electronic industry has enjoyed as a result of device scaling, we need more sophisticated EDA solutions to deal with both of these challenges.”

ESL is responding to the growth of design complexity and the need for earlier and more thorough design verification, including low power characteristics, and software integration.

The Design-to-Silicon division is addressing the issues of IC implementation which result not only from the increase in design complexity and devices sizes, but also from increasing sensitivity of the manufacturing process to physical design decisions, a phenomenon often referred to as “manufacturing variability.”

Although the term “Design-For-Manufacturing” reflects the need to consider manufacturability in design and to optimize for both functional and parametric yield, it is important to emphasize that DFM is not simply an additional tool or discrete step in the design process, but rather an integration of manufacturing process information throughout the IC implementation flow.

With single threading, we can no longer handle designs over 100 million gates. Of course, at 45nm, you can do a 100mn gates. That rewriting process is another issue that is also slowing out. It would be interesting to see how is Mentor handling this.

According to Sawicki, Mentor has incorporated sophisticated multi-threading and multi-processing technologies into all of its performance-sensitive applications, from place-and-route, through physical verification, resolution enhancement and testing.

He says, “Our tools have a track record of impressive and consistent and performance and scalability improvements, which is why we continue to lead the industry in performance.”

In addition to merely adding multi-threading and support for multi-core processors, Calibre products have a robust workflow management environment that automatically distributes the processing workload in the most efficient manner across any number of available clustered computing nodes.

Mentor’s Olympus-SoC place-and-route is inherently scalable due to its advanced architecture which includes an extremely efficient graph representation for timing information, and a very concise memory footprint. In addition, all the engines within Olympus-SoC can take advantage of multi-threaded and multi-core processors for high performance. These features enable Olympus-SoC to handle 100M+ gates designs in flat mode without excessive turnaround time.

Mentor’s ATPG tools are also designed to operate in multiprocessing mode over the multiple computing platforms to reduce test pattern generation time. In addition, Mentor test pattern compression technology reduces test pattern volume and test time, making it feasible to fully test 100M gate devices and maintain product quality without an explosion in test cost.

With EDA is starting to move up to the system level, will this make EDA less dependent on the semiconductor world?

Sawicki agrees that there are challenges at both the front end and back end of the electronic products design and manufacturing life cycle. Both of these opportunities are growing. In addition, developments like multi-level (3D) die packaging, through-silicon via (TSV) structures and other non-traditional techniques for device scaling are pushing system and silicon design issues closer together.

Reaching the 22nm node will require highly compute intensive EDA techniques for physical design to compensate for limitations in the manufacturing process. Beyond that, we could see a major shift to new materials and manufacturing techniques that would open new green fields for EDA in the IC implementation flow.

EDA going forward
How does Mentor see the EDA industry evolving, going forward?

Sawicki adds: “There are three key trends to watch. Firstly, for design to remain affordable at the leading edge, we need to enable radical increases in productivity. Electronic System Level (ESL) design is the key here, allowing designers to move to a new level of abstraction for both design and verification.

“Secondly, the challenges of manufacturing a well-yielding and reliable device as we move to 22nm will require a far more sophisticated physical implementation environment—one that accounts for physical effects in the design loop, and accounts for manufacturing variability in it’s optimization routines.

“Finally, the manufacturing challenges also open significant opportunity for EDA in the manufacturing space. A great example of this is the September 17, 2008 announcement we did with IBM on a joint development program to enable manufacturing at the 22nm node.”

Finally, given the roles already defined by Magma and Synopsys in solar, is there an opportunity for EDA in solar/PV?

According to Sawicki, as the photovoltaic devices have very simple and regular structures, most of the opportunity for EDA is not in logic design tools, but in material science, transistor-level device modeling, and manufacturing efficiencies with a focus on conversion efficiency and manufacturing cost reduction.

EDA’s role in solar will be in the newer areas related to Design-for-Manufacturing and other manufacturing optimizations, he concludes.

Our last discussion on DFM will follow in a later blog post!

Synopsys' Dr Chi-Foon Chan on India, low power design and solar

There have been reports about the troubles within the EDA industry in recent times, especially those related with quarter sales. Interestingly, Synopsys has been the one sailing along fine! If that’s not enough, it made its intention known of playing a role on the solar/PV segment, an area where lot of investments have been happening!

Given this scenario, I was fortuitous enough, rather, extremely lucky to be able to get into a conversation with Dr. Chi-Foon Chan, President and Chief Operating Officer, Synopsys Inc., during his recent visit to India.

On the state of the global semiconductor industry, he said, it was somewhere now in the low 10s [well below 10 percent]. The EDA industry is currently tracking below that level. However, Synopsys has been growing at around 10 percent. He said, “The technology challenges today are very high.”

Synopsys has a substantial number of R&D population based out of India. Giving his assessment of the Indian semiconductor industry, Dr. Chan added: “Our main interest in India is largely talent and the academia. India can very well get more into the product development side. Even the outsourcing of designs have increased. Our capabilities, of the Indian team, have also increased.”

As with any good semiconductor ecosystem, the Indian industry also needs a proactive industry association, a role played to near perfection by the ISA (India Semiconductor Association). Acknowledging the ISA’s role, Dr. Chan said, “The ISA has also formed a very cohesive team.”

There is little doubt about India’s growing importance in technology strengths and managerial leadership. Dr. Chan added: “We are more on the high-end side and also track what others design. In India, the profiles of designs are definitely high-end in nature. This is largely due to the presence of a large number of MNCs. A very high percentage of designs are in the 45nm and 65nm process technology nodes.”

There is another significant indicator of India’s growing importance, and that is the huge rise in the attendance of the SNUG. In 2000, this event attracted 180 people. However, in 2008, the SNUG attracted over 2,000 people.

Moving India to next level
Given the very high level of commitment on Synopsys’ part toward India, there was a need to find out from Dr. Chan what exactly India needs to do to move to the next level in the value chain in the semiconductor ecosystem.

He advised: “India can do two to three things. One, for the system to grow, you need the government, academia and industry to grow together. India has all of the ingredients required to drive products.”

Comparing India with China, he highlighted the fact that while in China, the local consumption was higher than local supply, that was not the case with India!

“Therefore, looking at merely the local market is not the only thing. Products developed here can also be targeted at the Middle East and Southeast Asia.” He was quite forthright in his analysis, adding: “Industries start when you find markets. The skill sets are already present here. There can well be multiple startups.”

Dr. Chan also touched upon the fab vs. fabless issue, noting that there could well be more of fabless companies in India. “Building a fab requires lot of capital. Also, consolidation will continue to happen.”

What role does Dr. Chan see Synopsys playing in the Indian context? He said: “Synopsys will continue to be a catalyst for the industry. A healthy design industry in India continues to help us. We also work well with the Indian universities. Having more people from the universities will always help. We also invest a lot in application support. The application team also trains others. I now look forward to seeing more fabless companies here and India to become even more global.”

On low power design
India is also a centre of expertise in low power design, given that low power is hugely important in today’s electronics ecosystem. Dr. Chan commented that low power has always been the number one design issue. It cannot be taken care of at one single stage.

He added: “A slightly new concept that has emerged is low-power verification. There are so many schemes for attacking low power, such as multiple voltage islands. We (Synopsys) are spending a lot of effort in low power.

“As a designer, you require detailed analysis. Low-power verification is now coming up. Another area is testing. As an example, if so much power is required, how do you have the power cut from the tool you are using to test? From a Synopsys point of view, we are involved in several points, such as front-end synthesis, testing, sign-off, verification, etc. We are trying to put in a whole lot of methodologies.”

Synopsys in solar
EDA may be able to help by lowering power requirements and leakage on better products. Especially, the Synopsys’ TCAD product can be used to create more efficient and effective solar cells. Now, this is not a new development anymore. Synopsys, along with Magma, have already made known their intentions about setting foot in the solar/PV space.

On the TCAD, Dr. Chan said: “We have a very strong position in the TCAD, commercially. Now, it is one of our most critical elements in high-performance. Our TCAD is among the strongest in the EDA industry.

“In solar, it does not have to be a complicated place-and-route, etc. From an entire solar industry point of view, we have now used some effort from TCAD into this space. Heat transfer issues, etc., are more in the EDA space.”

I will continue my conversation with Synopsys on its solar initiative sometime later. Keep watching this space, folks

EVE betting strong on Indian semicon industry

I have known Montu Makadia, Director and Country Sales Manager, EVE Design Automation Pvt. Ltd, since his days at eInfochips. It was interesting to learn more about the company and its strategy for India over the coming years.

For those who came in late, EVE offers a broad range of hardware-assisted verification solutions on the market, from acceleration to fast emulation and prototyping, with the most cycles per dollar. EVE products lead to a significant shortening of the overall verification cycle of complex integrated circuits and electronic systems design.

EVE products also work in conjunction with popular Verilog and VHDL-based software simulators from Synopsys, Cadence Design Systems and Mentor Graphics. Its sales headquarters in the United States is in San Jose, California. EVE’s manufacturing, R&D and corporate headquarters is located in Palaiseau, France.

Estimating the Indian semiconductor industry, Makadia said the global semiconductor market continues to grow, driven by the demand for consumer-oriented electronic devices. The Indian semiconductor industry, in particular, appears quite strong and is an attractive market opportunity for EVE.

“That’s because of its push into digital media, telecom and mobile communications markets that presents tremendous growth opportunities for companies such as EVE,” he said.

According to him, industry watchers should see strong growth in semiconductors in India in the coming years, propelled by smaller process technologies, multi-core architectures and the ever-increasing software content in system-on-chips (SoCs). With more SoC designs, the demand increases for hardware/software co-verification solutions.

EVE’s belief in the Indian market has been so strong that EVE Design Automation Pvt. Ltd., a wholly owned subsidiary based in Bangalore, was formed in 2007. EVE DA markets and supports the Zebu (for ‘zero bugs’) hardware-assisted verification platforms of accelerators, emulators and FPGA prototypes.

ZeBu enhances SoC performance
So, how exactly does ZeBu help analyze, benchmark and measure performance of the system-on-chip (SoC) over realistic scenarios?

Makadia said: “We have been really successful last year promoting the Zebu based emulation platform. Our existing customers, as well as new prospects in India, have shown great interest and recognized real value in adopting Zebu, not only for hardware verification but also for hardware and software co-verification.

“The Zebu platforms enable software validation and co-verification in a range of several megahertz, thus replacing the deployment of ASIC or prototype boards. For instance, we booted operating systems, e.g., Linux and WinCE, on processors designs mapped into ZeBu emulation platforms at 10-20 megahertz using a transactor-based verification methodology.”

How can EVE’s ZeBu be the choice of startups who need first-pass silicon success? Makadia added that startups in need of first-pass silicon success and designers worldwide have found that emulation tools such as Zebu are the only option for debugging hardware and testing the integration of hardware and software within complex SoCs.

He noted: “This is especially true when the task calls for executing billions of cycles in less than one hour and there’s a need for full visibility into the hardware. The ability to track hardware and software interaction offered by Zebu is considered a plus.”

ZeBu helps to analyze benchmark and measure SoC performance with realistic scenarios by running at speeds well above one megahertz. It is capable of executing complete test scenarios within an acceptable timeframe and just shy of running in real time.

This is interesting, and further examination needs to be done to evaluate how the emulation segment is performing and where it is evolving, especially, in India?

Makadia said: “After several years of stagnation, the overall market for emulation has been growing due to escalating complexity in hardware and in embedded software. Other factors have made emulators attractive once again. They run faster, are easier to use, have smaller footprints and are cheaper than older generations.”

The growth trend for emulation and hardware/software co-verification solutions will continue in the foreseeable future, especially in India.

Speaking on EVE’s overall strategy, he added that the company will continue to introduce even better performing emulation platforms through innovative architectures and enhanced supporting software to increase adoption by all market segments of the electronics industry.

Further, EVE is evaluating strategic partnerships and possible mergers with various synergistic companies to expand the attraction of its offerings.

Indian fab policy gets 12 proposals; solar dominates

Just about 10 odd days ago, I had blogged about building-integrated photovoltaics (BIPV)! I had also mentioned how solar/PV will be the next big story in India, with BIPV right up there at the very top!

Well, according to a published report on India Infoline, the Indian semiconductor and fab policy has attracted 12 major proposals, worth a whopping Rs. 93,000 crores!

A Press Information Bureau (PIB) release says that the Department of Information Technology (DIT), Government of India, has set up a panel of technical experts to evaluate the proposals.

The promoters will come up to the Appraisal Committee for sanction of subsidy under the scheme once they have reached the threshold limit of investment, as indicated in the guidelines of the Special Incentive Package Scheme.

A majority of these proposals — ten (10) — are for solar/PV. One proposal is for a semiconductor wafer — from Reliance Industries worth Rs. 18,521 crores, and another for TFT LCD flat panels — from Videocon Industries, worth Rs. 8,000 crores.

The 10 proposals for solar/PV are from: KSK Surya (Rs. 3,211 crores), Lanco Solar (Rs. 12,938 crores), PV Technologies India (Rs. 6,000 crores), Phoenix Solar India (Rs. 1,200 crores), Reliance Industries (Rs. 11,631 crores), Signet Solar Inc. (Rs. 9,672 crores), Solar Semiconductor (Rs. 11,821 crores), TF Solar Power (Rs. 2,348 crores), Tata BP Solar India (Rs. 1,692.80 crores), and Titan Energy System (Rs. 5,880.58 crores).

Does the Indian solar/PV story now start making some sense? It is very much in line to become the next big success story for India after the Indian telecom story!

Evidently, Reliance Industries is the major player in all of this, having proposed both a semicon wafer fab as well as a solar/PV fab. Lanco Solar, Solar Semiconductor, Signet Solar, Videocon, and PV Technologies are some of the other big players proposing to enter the Indian semiconductor/fab space.

Well, this is really great news for the Indian semiconductor industry! Further, it comes close on the heels of the announcement of the 3G spectrum policy and MNP policy by the government of India.

A few weeks ago, Dr. Madhusudan V. Atre, president, Applied Materials India, had mentioned that taking the solar/PV route was perhaps, a practical route for India to enter manufacturing. How true are those words!

Late June, I too had proposed, among others points, that Karnataka (and other Indian states) look at having some solar/PV fabs.

Dr. Pradip K. Dutta, Corporate Vice President & Managing Director, Synopsys (India) Pvt Ltd had also mentioned late June that it was too early to write off the Indian fab story. We now have the answer to that question of having fabs in India!

All of this should also excite those investors looking to enter India. The huge interest and subsequent proposals for solar/PV can also lead to India having some of its own solar farms as well!

The India Semiconductor Association should be congratulated for having made this happen. It is soon going to a year since the Indian government had announced the semiconductor policy. Now, with these mega proposals in place, maybe, we will see more investors in the Indian semicon and solar/PV fab spaces.

Top 10 Indian semicon companies review
Another interesting thought! Last year, around this time, I had prepared a list of the Top 10 Indian semiconductor companies. This particular blog has been among the most accessed.

Perhaps, a review is in order! Besides, several Indian players are beginning to make a mark, like Cosmic Circuits, SemIndia, etc. The list of August 2007 mostly had Indian design services companies. This feature of Indian design services companies dominating a top 10 list will probably continue for some more time, till all of these proposals bear fruit into concrete, productive fabs.

I am sure, with those mega investments coming into the Indian semicon wafer IC fab and solar/PV fabs, most of the companies would soon figure in any top 10 list!\

Surely, 2009 should be quite exciting as all of this means a very positive future and outlook for the Indian semiconductor industry.

Why 3G operators can't ignore TD-SCDMA

Come Beijing Olympics, and China will be showcasing the TD-SCDMA (Time Division-Synchronous Code-Division Multiple Access) technology. Largely unheralded, and spoken about by relatively few, TD-SCDMA may well surprise the telecom industry and pundits.

In fact, it is not even well known that the Ministry of Information Industry (MII) in China had allocated a total frequency of 155MHz for TD-SCDMA way back in Q3 of 2002. Back then, Lothar Pauly, then member of the Group Executive Management of Siemens Information and Communication Mobile had said that the allocation of frequencies for TD-SCDMA in China marked “a milestone in the standard’s development.” Siemens mobile has been developing 3G technology jointly with the China Academy of Telecommunications Technology (CATT/Datang) since 1998.

As per the TD-SCDMA Forum, China Mobile has announced its TD-SCDMA terminal timetable. Apparently, in China Mobile‘s second round of TD-SCDMA terminal bidding, ZTE has won orders for 61,000 handsets and Samsung for 20,000 handsets.

Also, the MIIT has established a 3G inter-ministerial co-ordination group. Li Yizhong, minister of the new Ministry of Industry and Information Technology (MIIT) in China, says that the ministry has established a 3G inter-ministerial co-ordination group to promote the commercial test and ensure the success of TD-SCDMA.

He says that the ministry should actively promote the commercial test of TD-SCDMA, further reform the system, and carry out the major scientific and technological projects. Relative officials are required to supervise the construction of TD-SCDMA base stations in Beijing to ensure the call quality of TD-SCDMA and ensure the trial operation of TD-SCDMA mobile phone TVs during the upcoming Olympic Games.

The minister has also issued orders to give full support to the implementation of measures and policies beneficial for the development of TD-SCDMA. The ministry should organize Chinese telecommunication units to realize better network optimization, supply special Olympic services, co-ordinate the interoperability between 2G and 3G, solve the problems in the commercial tests, and to ensure the initial success of TD-SCDMA.

All of these developments reminds and takes me back to 2000, when TD-SCDMA was just starting to make the rounds. A good friend, Shih-ying Tan from Siemens Hong Kong, called me up to discuss this technology! Subsequently, it led to visit to Munich, to see the technology first hand!

Here are excerpts from a discussion I had, back in August 2001, with Klaus Maler, who was general manager, TD-SCDMA, for Siemens Information and Mobile Communications in Munich, Germany, at that point of time (in pic). I was serving Wireless Week, US, as its Asia-Pacific editor. Some or most of this may read a bit outdated, but it is still worth a read for those keen on TD-SCDMA.

TD-SCDMA, a 3G technology co-developed by Siemens AG and the China Academy of Telecommunications Technology, is said to be the only technology suitable for TDD (time division duplex) bands. In addition to being more spectrally efficient for both symmetrical and asymmetrical data services, it is capable of dealing with hot spot scenarios. Some TDMA operators reportedly are considering it as an option for migrating to 3G, and once deployed on the mainland of China, it is likely to reach the economies of scale that would make it attractive to mobile operators worldwide.

Acceptance by carriers
What are the chances that TD-SCDMA will be accepted by carriers, given that it is a TDD technology while wideband-CDMA and CDMA2000 are FDD (frequency division duplex) technologies? Isn’t TDD in a minority here?

Maler had replied that TD-SCDMA, as well as W-CDMA, uses GSM MAP [manufacturing automation protocol]. This means that it is very likely to have affordable GSM/W-CDMA or GSM/TD-SCDMA dual-mode or GSM/TD-SCDMA/W-CDMA triple-mode handsets. On the other hand, an exotic GSM/CDMA2000 handset should support two different MAPs–GSM and IS-833. Dealing with such complicated and expensive handsets does not encourage GSM operators to adopt a CDMA standard.

As TD-SCDMA is TDD based, it offers optimum spectral efficiency for both symmetric and asymmetric data services. Certainly, carriers won’t ignore this aspect. On an international scale, TD-SCDMA is the only technology suitable for the TDD bands, assigned by regulators worldwide and already have been auctioned in Europe. So TD-SCDMA, being an accepted standard worldwide, approved by the ITU and standardized in the 3GPP (Third-Generation Partnership Project), is definitely not in a minority.

Were there any chances that TD-SCDMA won’t get locked in like another TDD standard, PHS, has in Japan? In response, Maler said TD-SCDMA is an accepted technology, while PHS is more of a local standard in Japan. Also, TDD frequencies have been allocated in most of the European countries. These are the two major reasons why TD-SCDMA has more potential.

Mainland China is already the largest mobile market now. TD-SCDMA will be deployed in China as a global standard, addressing all sizes of cells, [so] the necessary effects of scale will be available for operators worldwide.

“We had discussed with mainland Chinese manufacturers a few years ago the advantages of combining TDD technologies with smart antennas. We studied this issue and this evolved into continuous improvement and actual development. This happened at a time when we were looking at the mainland Chinese market as a major focus. Last year, when we realized that TD-SCDMA had good potential, we started to introduce it into the 3GPP. Now it has been accepted as a global standard,” he said.

According to him, TD-SCDMA has a very bright future, [although] operators may go for a combination of technologies. TD-SCDMA allows operators to add spectrum for voice services using their core GSM networks. The version we are talking about for the launch in mainland China is based on a GSM core network. This will later evolve into a UMTS core network. We started developing the technology three years late, [so you could] say that TD-SCDMA is three years more modern than the other technologies. Now, we are all having trials simultaneously.

Is there a compelling case for TDMA operators to go the TD-SCDMA route? At the moment [this is 2001 end, remember], most TDMA operators in United States, for example, Cingular Wireless, AT&T Wireless and VoiceStream Wireless, are embracing GSM, thereby, acknowledging it as a worldwide standard. They are also committed to adopting the following migration path–TDMA-GSM-GPRS-EDGE-UMTS– following the footsteps of European operators.

Both of the UMTS alternatives –- W-CDMA and TD-SCDMA -– are being taken into consideration by TDMA operators, either as a complementary or an alternative solution. In particular, American TDMA operators believe that TD-SCDMA, thanks to its higher data transmission rate and its capability to deal with asymmetrical traffic and hot spot scenarios, is an interesting technology. The 1.6MHz bandwidth [it uses] will certainly ease the spectrum allocation in the already crowded spectrum currently available in the United States.

Most of the TDMA operators are moving to the GSM-GPRS-EDGE-W-CDMA route. It’s not easy to get FDD spectrum in the United States and it will become even more difficult in the future. This is a very good opportunity for a TDD technology like TD-SCDMA.

TD-SCDMA in Europe
Were there any plans to implement TD-SCDMA in Europe, and especially Germany, given that Siemens has been playing an active role in developing this technology?

In Europe, TD-SCDMA will be deployed with capacity-enlargement purpose
s in W-CDMA networks in hot spot scenarios. By that time, TD-SCDMA will already be a mature technology and will have derived benefits from the mainland Chinese experience.

Most of the operators are now focusing on W-CDMA. They can consider TD-SCDMA to enhance services later on. We are speaking with several operators in Europe. They have been surprised and have actively responded [because] they can see that the chances for TD-SCDMA to succeed have improved considerably. Operators that had not chosen Siemens for some reason now have decided to take another look at us.

And why aren’t GSM operators elsewhere showing interest in this technology? Instead, they have been opting for W-CDMA? In the very beginning in Europe, around 1998, TDD was conceived as a technology only for micro and picocell coverage. Consequently, it was considered interesting only in a second phase of the UMTS deployment as a capacity enlargement. Spectrum was assigned and licenses were bought bearing this in mind.

As TD-SCDMA is also able to cover large cells, the momentum behind it is increasing considerably and we are getting quite a lot of interest from European operators of merging TDD activities into this technology.

TD-SCDMA is quite a good alternative. Also, if an operator already has W-CDMA and adds TD-SCDMA, or it’s the other way around, it’s quite a good combination. Very soon, carriers will notice capacity shortages, especially for the more powerful applications. Facing the fact that they are wasting bandwidth, in terms of asymmetrical traffic, TDD is the technology of choice. The combination of both technologies — W-CDMA and TD-SCDMA — may apply in most countries, even here in Europe.

By the way, there used to be LinkAir’s LAS-CDMA (Large Area Synchronized Code-Division Multiple Access). LAS-CDMA was also said to offer a higher spectral efficiency and moving speed, thus providing better support for mobile applications. Its asymmetric traffic, higher throughput, and smaller delay provide also improved IP support. A LAS-CDMA TDD variant is compatible with systems such as TD-SCDMA.

I had written about LAS-CDMA back in 2000, but have been unable to find the link. Even there’s no update on this technology. Would be great if folks could update me on LAS-CDMA.

Lastly, I need to thank Chi-Foon Chan, president and COO of Synopsys, who I recently met on the sidelines of the Synopsys SNUG event. Chan discussed TD-SCDMA and LAS-CDMA briefly, while touching upon the semicon/EDA industry. But, more of that later!

Tackling low-power design issues — Synopsys

Managing power efficiently is not a choice, but an imperative. Semiconductor content is increasing everywhere, and in fact, consumers and globalization are driving the semiconductor content in electronic systems.

A glance at the ecosystem pyramid reveals that the global electronics industry stands at US$3,200 billion, semiconductors at US$274 billion, equipment and materials at US$86 billion, and EDA at US$4.4 billion. EDA is at the heart of the electronics industry.

Subhash Bal, country director, Synopsys (India) EDA Software Pvt. Ltd, says that for low power imperatives, it is important to look at systemic factors. Energy usage and carbon emissions, especially, have been growing alarmingly, and will continue to do so for quite some time. This is largely due to uncontrolled consumption of devices and other electronic equipment. “We need to support energy usage without carbon emissions. In that respect, solar is a good solution,” he adds.

Computing is energy intensive by nature. Consider these stats — approximately 1 billion of the world’s PCs are switched on for nine hours per day, requiring 95,000MW. And of the US$250 billion spent globally each year powering computers, about 85 percent of that energy is wasted, while the computer stands idle.

Today, more devices and gadgets are being introduced, with more features and at lower prices. All of these devices demand a huge amount of battery power. Speed increases at the expense of energy consumption. Leakage has also become a major issue. There is therefore a growing need to solve power-related problems.

The Synopsys Sentaurus
Synopsys’ Sentaurus optimizes a device’s power. It also addresses photovoltaics. The Sentaurus process is an advanced 1D, 2D, and 3D process simulator for developing and optimizing silicon and compound semiconductor process technologies.

Created by combining features from Synopsys and former ISE TCAD products, together with a wide range of new features and capabilities, Sentaurus is a new-generation process simulator for addressing the challenges found in current and future process technologies. “The Sentaurus takes care of the processing part. It does modeling, 2D/3D simulation, etc. It can be applied to both semiconductors and solar,” says Bal.

Eclypse low-power solution
Synopsys’ goal is to deliver the most comprehensive solution, enabling designers to build the most advanced, low power chips and systems in the world. In the hope of achieving this, it has introduced the Eclypse low-power solution. Sharat D Kaul, sales and marketing manager, Synopsys India, highlights the fact that the Eclypse looks at the design side specifically.

The silicon-level concerns include factors such as more functionality, more computing power, limited power budget, design complexity, verification complexity, testing, reliability and schedule. System-level concerns include factors such as battery life, system cooling, reliability, packaging cost, operating cost, air conditioning cost, carbon footprint and green initiatives. Most design teams are both overwhelmed and under prepared.

The Eclypse low power solution is aimed at addressing such needs. It provides an alignment of technology, IP, methodology, services and industry standards — geared to meet the challenges of advanced low power designs.

Eclypse supports the industry-standard Unified Power Format (UPF) language, used to capture low power design requirements. It offers low power education programs, end-to-end UPF support, multi-voltage verification with assertions, automated clock tree synthesis, and automated power switch optimization.

Premature to write off Indian fab story: Dr. Pradip Dutta

The previous blog was focusing on SemIndia and the notice it has received on the Fab City in Hyderabad, along with NanoTech. BV Naidu, a friend and an industry colleague, has put up a strong front, and is trying his best to ensure things get going in the IC wafer fab space in India. Best of luck to him and SemIndia. India needs a fab, much more than ever, now.

I also happened to have a brief chat with Dr. Pradip K. Dutta, Corporate Vice President & Managing Director, Synopsys (India) Pvt Ltd, another friend and an industry colleague. Although from the EDA industry, Dr. Dutta has great thoughts and ideas regarding the future of semiconductors in India.

According to him, building wafer fabs in India involves an element of national pride and should also make business sense, simultaneously. The government has to look at fabs from a national policy perspective. If there were any company breaking ground in India, to build a clean-room, we would have known, he states, which is very correct.

We all know that a fab is a highly capital intensive project. He says: “I hope we can see some concrete proposals by this time next year. It is too premature to say that the Indian fab story is disappearing.”

There is a need to bear in mind that fabs in India have a three-year window. So, there is no reason for getting worked up right now, as the window is still there and existing. Dr. Dutta adds: “The business people will only open up their cards in the final stages. I have reasons to believe by summer of 2009, there will be some actual stakeholders.”

A fab is a very economically complex business. In the next five-10 yrs, there is a strong feeling that there may be only three to four companies globally, as IDMs, and the rest move into foundry. Dr. Dutta stresses: “To expect India will have a 5bn, 45nm, capable fab is something that needs to be examined. The business case has to be the driver.”

The semicon policy has definitely been a good start. What has since happened since that the ancillary manufacturing industry has been taking advantage of the policy.

“The government is quite optimistic that as we reach next year, by this time, companies will firm up their plans, as the industry window is three years. We believe that concrete proposals will come in by that time,” reiterates Dr. Dutta.

The government wants to see a state-of-the-art facility come up as well. He notes: “Maybe, 50 percent of all ICs sold globally, can be built on 0.25-micron technology. However, under the current semicon policy, we want to encourage state-of-the art manufacturing.”

Given the current global economic scenario, it will take real effort on part of all the stakeholders and come up with a wafer IC fab. India seriously needs a fab! There’s a huge market out there, which needs to be tapped. Delays will only add to our slipping back.

Semicon special: Global and Indian scenarios, design trends

I’ve been blogging on semicon for some time now, and it is also going to be a year since the CIOL Semicon site was launched.

This special edition looks at the global semiconductor scenario — how is the industry dealing with the ‘deep trauma’ it finds itself in, along with certain forecasts. Will the recession bring the industry down, or is there light at the end of the tunnel? We also look at some predictions made in the past and evaluate where the semiconductor industry stands today.

In the Indian context, the special analyzes India’s growing might in the global semiconductor market, the emergence of India as an embedded superstar, the growing strength of the Indian design services segment, and a quick look at how planners need to take the semicon policy forward.

The special also addresses some leading design trends, such as the use of graphical system design for embedded control systems, trends in video compression, and why designers and developers need to go parallel. It also touches on some recent developments in 22nm.

All articles can be found on the CIOL Semicon site. Some of the posts are available on my blog as well. Enjoy!

Global Semiconductor Market Scenario

1. Top 10 global semicon predictions: where are we today
While the chip industry is equipped to take on the challenges ahead, do watch out for weaker DRAM and NAND markets.

2. Semicon likely to grow 12pc in 2008
If there will be an economic recession, the chip industry (but not all firms) is in the best shape possible to weather the ensuing storm.

3. Semi trends 2008: Fab spend lower, ASPs stabilizing
The call on global fab spend was for a 10 percent reduction, and this is now getting to be closer to 20 percent.

4. Global semicon to grow 4.9pc
These forecasts are based on April’s WSTS sales numbers, as per the Cowan LRA (Linear Regression Analysis) model.

Indian Semiconductor Market Scenario

1. India’s growing might in global semicon
India is fast becoming the world’s destination, and increasingly the source too, for semiconductors.

2. Indian design services to touch $10.96bn by 2010
Total design services market in India is said to have grown at 21 percent year on year.

3. Indian semicon industry creating its niche
The Indian semiconductor industry has established itself as a leading provider for design services outsourcing.

4. Indian semicon needs concrete planning
India should produce a good plan to take semiconductors forward and be realistic about what can be done.

5. India the emerging embedded superstar
We are witnessing a strong trend from companies slowly moving from ‘Service Only’ model to ‘Service + Product/IP’ model.

6. Emerging trends in embedded market
High-performance, low-power embedded systems are moving to platforms based on multicore and mobile processors with low thermals.

7. IBM-Telelogic to extend embedded offerings
Acquisition of Telelogic fortifies Rational development at India Software Lab, opens door for company to gain foothold in embedded.

8. EDA healthy and growing in India
Consumption of EDA technologies is growing in regions outside of the US and Europe.

Semiconductor Design Trends

1. Graphical system design for embedded control systems
Graphical system design (GSD) is a revolutionary approach to embedded design that blends intuitive graphical programming and flexible commercial off-the-shelf (COTS) hardware.

2. Video compression: trends in encoding/decoding chips
High-quality video transmission is creating challenges for designers, and this article seeks to address these challenges.

3. Be parallel, or perish!
Parallelism offers new doors, and creativity is required to open these new doors, says Intel.

4. Fascinating developments in 22nm!
These augur well for the global semiconductor industry, even though the field could get much narrower.

Indian semicon needs concrete plans

The Indian semiconductor market is still in a nascent stage. In the Indian context, while we are very good in design services, we have yet to achieve the required capability to build products.

In this context, Subhash Bal, Country Director, Synopsys (India) EDA Software Pvt. Ltd says: “One has to first understand the dynamics of the semiconductor market. The key is: if you grow a market here, it will also grow somewhere else. That’s where the trick lies!”

The Indian semiconductor industry really needs to figure out what will work! “It would be better to think about solving a particular problem, which will go on to solve a bigger problem for India. There is also a need to build incentives to go along with al of this,” adds Bal.

He states: “We should produce a plan to take semiconductors forward in India. We need to be realistic about what we can do with the semiconductor industry. India should better be up there, at the top, in terms of technology as well. For example, RFID can be used in a whole range of applications.”

Way forward
What can be the way forward for the Indian semiconductor industry? First, there is a need to create a plan for Indians residing in the USA to return home and start something. They should be offered a lot of incentives as well. Next, there is a need to allow developing schemes where Indian applications become the focus, especially for high-volume government applications, such as traffic light controls, ID cards, toll tax applications, etc.

“Such things will only trigger demand. It will also see the rise of Indian product companies, and later, those will grow into semiconductor companies,” advises Bal.

Indian fab story disappearing?
Is the Indian fab story disappearing from sight? Not exactly! There will be a lot of solar fabs coming up, while it is still early days for wafer IC fabs. Fabs for PV cells are relatively easy to set up. Undoubtedly, PV has a huge market potential.

On the subject of fabs, Bal says: “The technique of management of fab technology is crucial. There should be some government schemes for smaller fabs as well. It does not matter whether these are 150mm or 180mm fabs. Indigenous applications can source simple applications, such as autorickshaw meters, toll tax applications, etc.”

Bal, like many others, believes that the next decade clearly depends on the youth of India. Therefore, this plan for semiconductors has to be long term — for about 25-30 years — and action oriented. This has to start from an end solution, and thereafter, semiconductors should be able to take off!

“Apart from such a plan, it is also important that sufficient attention is given to developing the right infrastructure. Infrastructure needs to be fixed as well. Should these be addressed, the semiconductor industry in India will likely take off,” adds Bal.

Globally, Synopsys has been growing steadily. In fact, the Q1-08 revenue is likely to close at $325 million. Synopsys India has a current headcount of over 600 employees, located in Bangalore, Hyderabad and Noida. The activities of the Hyderabad center is global in nature.